> one more question. It's not clear to me how > the irm pool stuff works. > > Who actually allocates MSI/X address/data values > when these pools are used/defined? > > Did I miss that part of the design or interface? This is more of an implementation issue. DDI interrupt framework just manages the interrupt pool (# of MSI/X vectors), but it is not responsible for assigning or programming any MSI/X address and data values. This project is not changing this part and it is still all done by the platform specific layers such PCIe nexus drivers (px, pci, npe).
Cheers GOVINDA
