Rocky wrote:
>> ssdt_1_CpuPm.dsl contains the following ASL for
>> \PR.CPU1:
>>
>> Scope (\_PR.CPU1)
>> {
>> Name (HI1, 0x00)
>> Name (HC1, 0x00)
>> Name (TLD1, 0x00)
>> Method (_PDC, 1, NotSerialized)
>> {
>> CreateDWordField (Arg0, 0x08, CAP1)
>> Store (CAP1, PDC1)
>> If (LEqual (TLD1, 0x00))
>> {
>> If (LEqual (And (PDC1, 0x0A), 0x0A))
>> {
>> If (And (CFGD, 0x02))
>> {
>> OperationRegion (IST1, SystemMemory,
>> DerefOf
>> Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
>> )))
>> (IST1, HI1)
>> }
>> Store (0x01, TLD1)
>> }
>> }
>> n particular, note the line that I've marked with the
>> arrow above. It's
>> checking to see if bits 1 & 3 are enabled in the PDC
>> and will load
>> cpu1ist if true. I believe this is the problem since
>> Solaris does not
>> enable bit 1. According to the Intel Processor
>> Vendor-Specific ACPI
>> enabling bit 1 indicates:
>>
>> if set, OSPM supports the C1 "I/O then Halt" FFH
>> sequence for
>> multi-processor configurations.
>>
>> Typically, I've seen PDC methods check to see if bits
>> 0 & 3 (0x9) are
>> enabled. These make a lot more sense given that they
>> are P-state related
>> bits:
>>
>> bit 0: if set, OSPM is capable of direct access to
>> Performance State MSRs.
>>
>> bit 3: if set, OSPM is capable of independent C1, P
>> state and T state
>> support for each processor for multi-processor
>> configurations.
>>
>> Not sure what to tell you. We do have folks working
>> on deep C-state
>> support and I know that as part of their work they
>> are intending on
>> enabling bit 1 of the _PDC. Once they integrate into
>> Nevada (I don't
>> know the time frame), I believe SpeedStep should
>> start working for you.
>> But really, I don't think that there is any reason
>> that your BIOS should
>> be checking the bit.
>
> Many thanks for your detailed and quick reply.
>
> Bit 1 of OSPM _PDC is for "C1"? C1E (CPU enhanced halt) is enabled in the
> BIOS, do you think this bit is being set because of that entry? I will
> experiment and see.
>
No. Bit 1 is not for C1E. C1E is a hardware feature that you really
don't want to disable. It should provide good power management savings
all on its own.
>
> This message posted from opensolaris.org
> _______________________________________________
> opensolaris-discuss mailing list
> opensolaris-discuss@opensolaris.org
_______________________________________________
opensolaris-discuss mailing list
opensolaris-discuss@opensolaris.org
