Hi, On Fri, Mar 23, 2012 at 07:39:19PM +0100, openwrt-devel-requ...@lists.openwrt.org wrote: > Message: 2 > Date: Fri, 23 Mar 2012 18:00:18 +0100 > From: Spyridon Tompros <stomp...@qualtek.eu> > To: openwrt-devel@lists.openwrt.org > Subject: Re: [OpenWrt-Devel] LANTIQ- EASY5072- UART0 problem > Message-ID: <4f6cac22.6030...@qualtek.eu> > Content-Type: text/plain; charset=UTF-8; format=flowed > > If the problem is HW it cannot become better anymore.
Extra dumb question: perhaps it would be doable to have some playful experiments with some ferrite:ish cover layers near affected traces? (not sure whether there would be any effect at such scale, but without trying there's no knowledge...) Given that the PCB's layout is completely broken already, matters probably cannot get worse :) Disclaimer: _not_ an experienced EDA engineer here :) Andreas Mohr _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
