2013/12/9 Felix Kaechele <fe...@fetzig.org>: > Hi there, > > I'm currently trying to figure out a way how to solve the following issue > elegantly (i.e. from the mach file): > > Target Device: WD My Net N750 (AR9344 based, with AR8327N switch) > > Problem: > The device powers down all the PHYs from within the bootloader (possibly to > prevent early LAN <-> WAN leakage, as the ports are on the same switch and > separated by VLANs only). > The PHYs are powered down by writing 0x800 (Set Bit 11 (POWER_DOWN) to 1) to > register 0x0 of each PHY from within the bootloader. > The PHYs cannot be read while powered down (but can be written). This > results in mdiobus_scan (drivers/net/phy/mdio_bus.c) reading bogus PHY IDs. > > Solution: > Power all PHYs back up by writing 0x1000 (Set Bit 12 (AUTO_ > NEGOTIATION) to 1) to register 0x0 of each PHY _before_ scanning the MDIO > bus for PHY IDs but _after_ resetting/initializing the bus.
I would believe that attempting a PHY reset through BMCR_RESET should bring us back into a state where the PHYs will be responding again. It does not look like there are other platforms upstream having this problem, but this does sound like we should be handling this. I just sent some patches upstream which attempt to consolidate the PHY reset: http://patchwork.ozlabs.org/patch/298274/ maybe you could use this, you would need to slightly relax the constraints in phy_init_hw(), basically issuing the reset through BMCR_RESET and then using phy_poll_reset(). > > I have attached a patch that works (but is a nasty hack). > > So now I have the question how to handle this in a way that would also be > acceptable for upstream. > I was hoping for some input from the ar71xx gurus on how to do this :) -- Florian _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
