Hi, I'm bumping again, this patch is necessary to make the gigabit switch work on the Mikrotik 951G-2HnD (tested on CC).
Thanks, Baptiste On Wed, Nov 25, 2015 at 06:18:29PM +0100, Baptiste Jonglez wrote: > Hi, > > Sorry to bump up the thread again. Is there anything blocking to merge > this patch? > > If it helps, there are user reports about setting different values of > ath79_eth0_pll_data.pll_1000 here: > > > https://wiki.openwrt.org/toh/mikrotik/rb2011uias#tracking_reported_experience_with_suggested_patch_for_the_5_gige_ports > > Thanks, > Baptiste > > On Sat, Nov 14, 2015 at 06:30:52PM +0100, Baptiste Jonglez wrote: > > Hi, > > > > On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote: > > > Fix pll_1000 value for eth0. Traffic would not flow from the eth0 > > > interface. The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to > > > also enable AR934X_ETH_CFG_RXD_DELAY. > > > > I can confirm that this patch works on CC on a Routerboard 951G-2HnD > > [http://wiki.openwrt.org/toh/mikrotik/rb951g_2hnd] > > > > Without the patch, CC installs fine, but the switch does not work (traffic > > seems to be able to flow out of the router, but nothing comes in). > > > > This is a router with the "new" chipset (AR9344 rev. 3). > > > > Is it possible to pull this patch, at least to trunk? Having it in CC > > would also be nice if another CC release is planned. > > > > Thanks, > > Baptiste > > > > > Signed-off-by: Davey Hutchison <dhutchi...@bluemesh.net> > > > > > > --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c > > > +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c > > > @@ -199,6 +199,7 @@ > > > return; > > > > > > ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | > > > + AR934X_ETH_CFG_RXD_DELAY | > > > AR934X_ETH_CFG_SW_ONLY_MODE); > > > > > > ath79_register_mdio(0, 0x0); > > > @@ -209,6 +210,7 @@ > > > ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); > > > ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; > > > ath79_eth0_data.phy_mask = BIT(0); > > > + ath79_eth0_pll_data.pll_1000 = 0x3e000000; > > > > > > ath79_register_eth(0); > > > _______________________________________________ > > > openwrt-devel mailing list > > > openwrt-devel@lists.openwrt.org > > > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > > > > > _______________________________________________ > > openwrt-devel mailing list > > openwrt-devel@lists.openwrt.org > > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > > _______________________________________________ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
pgpYESz6xCKfA.pgp
Description: PGP signature
_______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel