Signed-off-by: Dieter Pfeuffer <dieter.pfeuf...@men.de> --- .../files/arch/powerpc/boot/dts/men_nm50.dts | 25 + .../files/arch/powerpc/boot/dts/men_nm50.dtsi | 625 +++++++++++++++++++++ .../arch/powerpc/boot/dts/men_nm50_ubootrw.dts | 13 + 3 files changed, 663 insertions(+) create mode 100644 target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dts create mode 100644 target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dtsi create mode 100644 target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50_ubootrw.dts
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dts new file mode 100644 index 0000000..4e0ce7b --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dts @@ -0,0 +1,25 @@ +/* + * MEN NM50 Device Tree Source + * + * Copyright (c) 2016 MEN Mikro Elektronik GmbH + * + * Based on P1022 Device Tree Sources from Freescale Semiconductor Inc. + * + * This is free software, licensed under the GNU General Public License v2. + * See /LICENSE for more information. + */ + +/dts-v1/; +/include/ "men_nm50.dtsi" + +/ { + soc@ff700000 { + spi0: spi@7000 { + flash@0 { + u-boot@0 { /* mtd0 */ + read-only; + }; + }; + }; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dtsi b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dtsi new file mode 100644 index 0000000..78f8ba2 --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50.dtsi @@ -0,0 +1,625 @@ +/* + * MEN NM50 Device Tree Source + * + * Copyright (c) 2016 MEN Mikro Elektronik GmbH + * + * Based on P1022 Device Tree Sources from Freescale Semiconductor Inc. + * + * This is free software, licensed under the GNU General Public License v2. + * See /LICENSE for more information. + */ + +/ { + model = "men,NM50"; + compatible = "men,NM50"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + spi0 = &spi0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1022@0 { + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + PowerPC,P1022@1 { + device_type = "cpu"; + reg = <0x1>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + }; + + localbus@ff705000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,p1022-elbc", "fsl,elbc"; + reg = <0 0xff705000 0 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0x0 0x0 0x0 0xee000000 0x02000000>; + }; + + soc@ff700000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1022-immr", "simple-bus"; + ranges = <0x0 0 0xff700000 0x100000>; + bus-frequency = <0>; // Filled out by uboot. + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,p1022-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <16 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,p1022-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + eeprom@54 { + compatible = "stm,24c04"; + reg = <0x54>; // 7-bit I2C address + }; + rtc@51{ + compatible = "epson,rx8581"; + reg = <0x51>; // 7-bit I2C address + }; + dtt@4d{ + compatible = "national,lm75"; + reg = <0x4d>; // 7-bit I2C address + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + status = "disabled"; + }; + + watchdog { + compatible = "linux,wdt-gpio"; + gpios = <&gpio3 11 0>; + hw_algo = "level"; + hw_margin_ms = <1000>; + }; + + spi0: spi@7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x7000 0x1000>; + interrupts = <59 0x2 0 0>; + interrupt-parent = <&mpic>; + fsl,espi-num-chipselects = <4>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <40000000>; + reg = <0>; + + u-boot@0 { /* mtd0 */ + reg = <0x00000000 0x00080000>; /* 512 KiB */ + label = "u-boot"; + }; + u-boot-env@80000 { /* mtd1 */ + reg = <0x00080000 0x00002000>; /* 8KiB (space reserved for secondary u-boot option) */ + label = "u-boot-env"; + }; + dtb@100000 { /* mtd2 */ + reg = <0x00100000 0x00010000>; /* 64 KiB */ + label = "dtb"; + }; + kernel@110000 { /* mtd3 */ + reg = <0x00110000 0x00800000>; /* 8 MB */ + label = "kernel"; + }; + rootfs@910000 { /* mtd4 */ + reg = <0x00910000 0x01600000>; /* 22 MB */ + label = "rootfs"; + }; + reserved@1f10000 { /* mtdX */ + reg = <0x01f10000 0x000f0000>; /* 960 KiB */ + label = "reserved"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; + interrupt-parent = <&mpic>; + }; + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; + interrupt-parent = <&mpic>; + }; + + dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <76 2>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <77 2>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <78 2>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <79 2>; + }; + }; + + gpio1: gpio-controller@f000 { + #gpio-cells = <2>; + compatible = "fsl,mpc8572-gpio"; + reg = <0xf000 0x100>; + interrupts = <47 0x2>; + interrupt-parent = <&mpic>; + gpio-controller; + }; + gpio2: gpio-controller@f100 { + #gpio-cells = <2>; + compatible = "fsl,mpc8572-gpio"; + reg = <0xf100 0x100>; + interrupts = <47 0x2>; + interrupt-parent = <&mpic>; + gpio-controller; + }; + gpio3: gpio-controller@f200 { + #gpio-cells = <2>; + compatible = "fsl,mpc8572-gpio"; + reg = <0xf200 0x100>; + interrupts = <47 0x2>; + interrupt-parent = <&mpic>; + gpio-controller; + }; + + tdm@16000 { + device_type = "tdm"; + compatible = "fsl,starlite-tdm"; + reg = <0x16000 0x1000 0x2c000 0x2000>; + clock-frequency = <0>; + interrupts = <63 8 62 8>; + interrupt-parent = < &mpic >; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,p1022-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma00: dma-channel@0 { + compatible = "fsl,ssi-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma01: dma-channel@80 { + compatible = "fsl,ssi-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + usb@22000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl-usb2-dr-v1.6","fsl-usb2-dr"; + reg = <0x22000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <28 0x2 0 0>; + phy_type = "ulpi"; + dr_mode = "host"; + }; + + mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; + + phy0: ethernet-phy@1 { +//dp@men: no rx-interrupts with this: interrupt-parent = <&mpic>; + interrupts = <3 1 0 0>; + reg = <0x1>; + }; + phy1: ethernet-phy@2 { +//dp@men: no rx-interrupts with this: interrupt-parent = <&mpic>; + interrupts = <9 1 0 0>; + reg = <0x2>; + }; + }; + + ptp_timer: ptimer@b0e00 { + compatible = "fsl,gianfar-ptp-timer"; + reg = <0xb0e00 0xb0>; + interrupts = <68 2>; + interrupt-parent = <&mpic>; + tmr-prsc = <0x2>; + cksel = <1>; + }; + + enet0: ethernet@B0000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + fsl,wake-on-filer; + clk-handle = <&etsec1_clk>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupt-parent = <&mpic>; + fixed-link = <1 1 1000 0 0>; + phy-handle = <&phy0>; + ptimer-handle = <&ptp_timer>; + phy-connection-type = "rgmii-id"; + queue-group@0{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB0000 0x1000>; + interrupts = <29 2 30 2 34 2>; + }; + queue-group@1{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB4000 0x1000>; + interrupts = <17 2 18 2 24 2>; + }; + }; + + enet1: ethernet@B1000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + clk-handle = <&etsec2_clk>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupt-parent = <&mpic>; + fixed-link = <1 1 1000 0 0>; + phy-handle = <&phy1>; + ptimer-handle = <&ptp_timer>; + phy-connection-type = "rgmii-id"; + queue-group@0{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB1000 0x1000>; + interrupts = <35 2 36 2 40 2>; + }; + queue-group@1{ + #address-cells = <1>; + #size-cells = <1>; + reg = <0xB5000 0x1000>; + interrupts = <51 2 52 2 67 2>; + }; + }; + + crypto@30000 { + compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", + "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x97c>; + fsl,descriptor-types-mask = <0x3a30abf>; + fsl,multi-host-mode = "dual"; + fsl,channel-remap = <0x3>; + }; + + power@e0070{ + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc", + "fsl,p1022-pmc"; + reg = <0xe0070 0x20>; + etsec1_clk: soc-clk@B0{ + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@B1{ + fsl,pmcdr-mask = <0x00000040>; + }; + }; + timer@41100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x41100 0x204>; + interrupts = <0xf7 0x2>; + interrupt-parent = <&mpic>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + message@41400 { + compatible = "fsl,p1022-msg","fsl,mpic-msg"; + reg = <0x41400 0x200>; + cell-index = <1>; + interrupts = <0xb0 2 0xb1 2 0xb2 2 0xb3 2>; + interrupt-parent = < &mpic >; + }; + + message@42400 { + compatible = "fsl,p1022-msg","fsl,mpic-msg"; + reg = <0x42400 0x200>; + cell-index = <2>; + interrupts = <0xb4 2 0xb5 2 0xb6 2 0xb7 2>; + interrupt-parent = < &mpic >; + }; + + msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 + 0xe1 0 + 0xe2 0 + 0xe3 0 + 0xe4 0 + 0xe5 0 + 0xe6 0 + 0xe7 0>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,p1022-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + }; + + pci0: pcie@ff709000 { + cell-index = <2>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xff709000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + /* pay special attention to the last property of the interrupt mask + * here. It specifies the polarity of the INTx in both the pci + * controller and the MPIC. On the P1022 and P1013 CPUs, INTx'es of + * the three PCI host controllers are internally shared with the + * external IRQ signals IRQ0-11 (PCI1 INTA->IRQ0, PCI2 INTA->IRQ4 + * and so on). On the A21 board, external IRQs 0:5 are used, IRQs + * 6:11 are used as GPIO (to control watchdog, etc). The reference + * manual specifies that in case the external IRQ lines are muxed to + * GPIO, active high polarity has to be used. In case the lines are + * indeed muxed to external IRQs, the polarity setting needs to + * reflect the polarity of the connected peripherals. That now is + * why in this device tree, the last specifier per interrupt is set + * to 1 (active low) for the first six interrupts, and to 2 (active + * high) for the later ones. */ + 0000 0 0 1 &mpic 4 1 + 0000 0 0 2 &mpic 5 1 + 0000 0 0 3 &mpic 6 1 + 0000 0 0 4 &mpic 7 1 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ff70a000 { + cell-index = <1>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xff70a000 0 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 0 1 + 0000 0 0 2 &mpic 1 1 + 0000 0 0 3 &mpic 2 2 + 0000 0 0 4 &mpic 3 2 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + + pci2: pcie@ff70b000 { + cell-index = <3>; + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0 0xff70b000 0 0x1000>; + bus-range = <0 255>; + /* <pci space > <pci addr hi> <pci addr low> <cpu hi> <cpu lo> <size hi> <size low> */ + ranges = <0x2000000 0x0 0xf0000000 0 0xf0000000 0x0 0x08000000 + 0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <16 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0 0 1 &mpic 8 2 + 0000 0 0 2 &mpic 9 2 + 0000 0 0 3 &mpic 10 2 + 0000 0 0 4 &mpic 11 2 + >; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + leds { + compatible = "gpio-leds"; + fault_led { + gpios = <&gpio3 13 1>; + }; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50_ubootrw.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50_ubootrw.dts new file mode 100644 index 0000000..8300e26 --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/men_nm50_ubootrw.dts @@ -0,0 +1,13 @@ +/* + * MEN NM50 Device Tree Source + * + * Copyright (c) 2016 MEN Mikro Elektronik GmbH + * + * Based on P1022 Device Tree Sources from Freescale Semiconductor Inc. + * + * This is free software, licensed under the GNU General Public License v2. + * See /LICENSE for more information. + */ + +/dts-v1/; +/include/ "men_nm50.dtsi" -- 1.9.1 _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel