TODO: the spi-mt7621 patches will break support for other targets
Signed-off-by: Rafaël Carré <fun...@videolan.org>
---
Changes since v1:
- Change sysc address, this seems to make resetting devices possible
- Remove watchdog driver as it is buggy and maybe not needed?
- Use pci-rt3883.c rather than vendor's pci.c
The pci-rt3883.c modifications will also break support for other targets.
I'm looking for feedback whether I should modify this driver like I did
the OpenWrt mediatek_eth_soc driver, or if I should write a new one.
The .dts structure for pci-rt3883 seems quite complex, it seems the
pci@10140000 node is a 'controller', pci@0 would be the host bridge,
and child nodes are the different slots?
I'm also confused by the pcie_ready checks in rt3883_pci_config_read
and rt3883_pci_config_write, I am not sure what they mean exactly.
Chuanhong Guo also advised me to write a new SPI driver, and a GPIO
driver is still missing.
It might also be possible to reset devices with ralink_reset_device(),
although it still needs some testing.
...-ralink-adds-support-for-RT6855A-SoC.patch | 686 ++++++++++++++++++
.../304-HACK-spi-mt7621-rt6855a-fix.patch | 35 +
...HACK-spi-mt7621.c-hardcode-frequency.patch | 69 ++
.../307-pci-rt3883-run-on-RT6855A.patch | 271 +++++++
4 files changed, 1061 insertions(+)
create mode 100644
target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch
create mode 100644
target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch
create mode 100644
target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch
create mode 100644
target/linux/ramips/patches-5.4/307-pci-rt3883-run-on-RT6855A.patch
diff --git
a/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch
b/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch
new file mode 100644
index 0000000000..50cb757da5
--- /dev/null
+++
b/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch
@@ -0,0 +1,686 @@
+From 5ba1ea2583e59d5d426412ea4f2982a40229ab13 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org>
+Date: Wed, 23 Dec 2020 14:16:37 +0100
+Subject: [PATCH 1/4] MIPS: ralink: adds support for RT6855A SoC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+TODO:
+- clean up dts file
+ some things are OpenWrt-only (mtd mac / eeprom)
+ some things might be removed (gdma?)
+ spi / pci should be moved to other commits
+ ethernet should go in OpenWrt dts
+
+All code is my own or based on existing in-tree files.
+
+Signed-off-by: Rafaël Carré <fun...@videolan.org>
+---
+ arch/mips/boot/dts/ralink/Makefile | 1 +
+ arch/mips/boot/dts/ralink/rt6855.dtsi | 207 ++++++++++++++++++
+ arch/mips/boot/dts/ralink/wap300n.dts | 22 ++
+ .../include/asm/mach-ralink/ralink_regs.h | 1 +
+ arch/mips/ralink/Kconfig | 13 +-
+ arch/mips/ralink/Makefile | 6 +-
+ arch/mips/ralink/Platform | 5 +
+ arch/mips/ralink/early_printk.c | 5 +-
+ arch/mips/ralink/irq-rt6855a.c | 172 +++++++++++++++
+ arch/mips/ralink/reset.c | 22 ++
+ arch/mips/ralink/rt6855a.c | 57 +++++
+ 11 files changed, 508 insertions(+), 3 deletions(-)
+ create mode 100644 arch/mips/boot/dts/ralink/rt6855.dtsi
+ create mode 100644 arch/mips/boot/dts/ralink/wap300n.dts
+ create mode 100644 arch/mips/ralink/irq-rt6855a.c
+ create mode 100644 arch/mips/ralink/rt6855a.c
+
+diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
+index 6c26dfa0a903..08c612190936 100644
+--- a/arch/mips/boot/dts/ralink/Makefile
++++ b/arch/mips/boot/dts/ralink/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
+ dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
+ dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
+ dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
++dtb-$(CONFIG_DTB_WAP300N) += wap300n.dtb
+ dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb
+ dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
+
+diff --git a/arch/mips/boot/dts/ralink/rt6855.dtsi
b/arch/mips/boot/dts/ralink/rt6855.dtsi
+new file mode 100644
+index 000000000000..d083d1d1b984
+--- /dev/null
++++ b/arch/mips/boot/dts/ralink/rt6855.dtsi
+@@ -0,0 +1,207 @@
++// SPDX-License-Identifier: GPL-2.0
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "ralink,rt6855a-soc";
++
++ cpus {
++ cpu@0 {
++ compatible = "mips,mips34Kc";
++ };
++ };
++
++ cpuintc: cpuintc {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ compatible = "mti,cpu-interrupt-controller";
++ };
++
++ palmbus@1fb00000 {
++ compatible = "palmbus";
++ reg = <0x1fb00000 0xe0000>;
++ ranges = <0x0 0x1fb00000 0x100000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ sysc@800 {
++ compatible = "ralink,rt6855a-sysc";
++ reg = <0x800 0x100>;
++ };
++
++ intc: intc@40000 {
++ compatible = "ralink,rt6855a-intc";
++ reg = <0x40000 0x100>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpuintc>;
++ };
++
++ memc@300 {
++ compatible = "ralink,rt6855a-memc",
"ralink,rt3050-memc";
++ reg = <0x300 0x100>;
++ };
++
++ watchdog@f0100 {
++ compatible = "ralink,rt6855a-wdt";
++ reg = <0xf0100 0x10>;
++ };
++
++ uart: uart@f0000 {
++ compatible = "ns8250";
++ reg = <0xf0000 0x30>;
++ interrupts = <0>;
++
++ clock-frequency = <921600>;
++
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ no-loopback-test;
++
++ status = "okay";
++
++ interrupt-parent = <&intc>;
++ };
++
++ gdma: gdma@30000 {
++ compatible = "ralink,gdma-rt2880";
++ reg = <0x30000 0x100>;
++ };
++
++ ethernet: ethernet@50000{
++ compatible = "ralink,rt6855a-eth";
++ reg = <0x50000 0x10000>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <21>;
++
++ mediatek,switch = <&esw>;
++ mtd-mac-address = <&factory 0xe000>;
++ };
++
++ esw: esw@60000 {
++ compatible = "ralink,rt3050-esw";
++ reg = <0x60000 0x8000>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <15>;
++ };
++
++ spi0: spi@c0b00 {
++ status = "disabled";
++
++ compatible = "ralink,mt7621-spi";
++ reg = <0xc0b00 0x100>;
++
++ //clocks = <&pll MT7621_CLK_BUS>;
++
++ //resets = <&rstctrl 18>;
++ //reset-names = "spi";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ //pinctrl-names = "default";
++ //pinctrl-0 = <&spi_pins>;
++ };
++ };
++
++ pci: pci@1fb80000 {
++ compatible = "ralink,rt3883-pci";
++ reg = <0x1fb80000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges; /* direct mapping */
++
++ status = "disabled";
++
++ pciintc: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpuintc>;
++ interrupts = <4>;
++ };
++
++ pci@0 {
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++
++ device_type = "pci";
++
++ bus-range = <0 1>;
++ ranges = <
++ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory
*/
++ 0x01000000 0 0x00000000 0x1f600000 0 0x00010000 /* io space */
++ >;
++
++ pci0: pci@0 {
++ reg = <0x2000 0 0 0 0>;
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ status = "okay";
++
++ bus-range = <0 1>;
++ ranges;
++ };
++ };
++ };
++
++};
++
++&spi0 {
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "Bootloader";
++ reg = <0x0 0x30000>;
++ read-only;
++ };
++
++ partition@30000 {
++ label = "Config";
++ reg = <0x30000 0x10000>;
++ read-only;
++ };
++
++ factory: partition@40000 {
++ label = "Factory";
++ reg = <0x40000 0x10000>;
++ read-only;
++ };
++
++ partition@50000 {
++ compatible = "denx,uimage";
++ label = "Kernel";
++ reg = <0x50000 0x7b0000>;
++ };
++ };
++ };
++};
++
++&pci0 {
++ wifi@0,0 {
++ compatible = "pci1814,3091";
++ reg = <0x0000 0 0 0 0>;
++ ralink,2ghz = <0>;
++ ralink,mtd-eeprom = <&factory 0x8000>;
++ };
++};
++
+diff --git a/arch/mips/boot/dts/ralink/wap300n.dts
b/arch/mips/boot/dts/ralink/wap300n.dts
+new file mode 100644
+index 000000000000..e8f81578a589
+--- /dev/null
++++ b/arch/mips/boot/dts/ralink/wap300n.dts
+@@ -0,0 +1,22 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++
++/include/ "rt6855.dtsi"
++
++/ {
++ compatible = "ralink,rt6855a-soc";
++ model = "Linksys WAP300n";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x20000 0x3fe0000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,57600";
++ };
++
++ pci@1fb80000 {
++ status = "okay";
++ };
++};
+diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h
b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+index 9dbd9f0870c9..0e947616fa43 100644
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -26,6 +26,7 @@ enum ralink_soc_type {
+ MT762X_SOC_MT7621AT,
+ MT762X_SOC_MT7628AN,
+ MT762X_SOC_MT7688,
++ RT6855A_SOC,
+ };
+ extern enum ralink_soc_type ralink_soc;
+
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 1434fa60f3db..312a8efee306 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -16,7 +16,7 @@ config RALINK_ILL_ACC
+ config IRQ_INTC
+ bool
+ default y
+- depends on !SOC_MT7621
++ depends on !SOC_MT7621 && !SOC_RT6855A
+
+ choice
+ prompt "Ralink SoC selection"
+@@ -36,6 +36,12 @@ choice
+ bool "RT3883"
+ select HAVE_PCI
+
++ config SOC_RT6855A
++ bool "RT6855A"
++ select HAVE_LEGACY_CLK
++ select HAVE_PCI
++ select MII
++
+ config SOC_MT7620
+ bool "MT7620/8"
+ select CPU_MIPSR2_IRQ_VI
+@@ -92,6 +98,11 @@ choice
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
++ config DTB_WAP300N
++ bool "WAP300N"
++ depends on SOC_RT6855A
++ select BUILTIN_DTB
++
+ endchoice
+
+ endif
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 26fabbdea1f1..2bb8ddd69dff 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -7,7 +7,10 @@
+ obj-y := prom.o of.o reset.o
+
+ ifndef CONFIG_MIPS_GIC
+- obj-y += clk.o timer.o
++obj-y += clk.o
++ifndef CONFIG_SOC_RT6855A
++ obj-y += timer.o
++endif
+ endif
+
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+@@ -22,6 +25,7 @@ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+ obj-$(CONFIG_SOC_MT7621) += mt7621.o
++obj-$(CONFIG_SOC_RT6855A) += rt6855a.o irq-rt6855a.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index 6095fcc334f4..143b88c5694b 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -22,6 +22,11 @@ cflags-$(CONFIG_SOC_RT305X) +=
-I$(srctree)/arch/mips/include/asm/mach-ralink/rt
+ load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
+ cflags-$(CONFIG_SOC_RT3883) +=
-I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
+
++# Ralink RT6855A
++#
++load-$(CONFIG_SOC_RT6855A) += 0xffffffff80020000
++cflags-$(CONFIG_SOC_RT6855A) += $(call
as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
++
+ #
+ # Ralink MT7620
+ #
+diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
+index eb4fac25eaf6..7aff0b8d5b82 100644
+--- a/arch/mips/ralink/early_printk.c
++++ b/arch/mips/ralink/early_printk.c
+@@ -16,6 +16,9 @@
+ #elif defined(CONFIG_SOC_MT7621)
+ #define EARLY_UART_BASE 0x1E000c00
+ #define CHIPID_BASE 0x1E000004
++#elif defined(CONFIG_SOC_RT6855A)
++#define EARLY_UART_BASE 0x1FBF0000
++#define CHIPID_BASE 0x1E000004
+ #else
+ #define EARLY_UART_BASE 0x10000c00
+ #define CHIPID_BASE 0x10000004
+@@ -74,7 +77,7 @@ void prom_putchar(char ch)
+ init_complete = 1;
+ }
+
+- if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
++ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628() ||
IS_ENABLED(CONFIG_SOC_RT6855A)) {
+ uart_w32((unsigned char)ch, UART_TX);
+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+ ;
+diff --git a/arch/mips/ralink/irq-rt6855a.c b/arch/mips/ralink/irq-rt6855a.c
+new file mode 100644
+index 000000000000..9f04d8af7037
+--- /dev/null
++++ b/arch/mips/ralink/irq-rt6855a.c
+@@ -0,0 +1,172 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ *
++ * Copyright (C) 2009 Gabor Juhos <juh...@openwrt.org>
++ * Copyright (C) 2013 John Crispin <j...@phrozen.org>
++ * Copyright (C) 2020 Rafaël Carré <fun...@videolan.org>
++ */
++
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++
++#include <asm/irq_cpu.h>
++#include <ioremap.h>
++#include <asm/mipsregs.h>
++
++#include "common.h"
++
++/* we have a cascade of 8 irqs */
++#define RALINK_INTC_IRQ_BASE 8
++
++/* we have 32 SoC irqs */
++#define RALINK_INTC_IRQ_COUNT 32
++
++#define RALINK_SOC_IRQ_TIMER 30
++
++enum rt_intc_regs_enum {
++ INTC_REG_MASK = 0,
++ INTC_REG_PRIO,
++};
++
++static u32 rt_intc_regs[] = {
++ [INTC_REG_MASK] = 0x04,
++ [INTC_REG_PRIO] = 0x10,
++};
++
++static DEFINE_SPINLOCK(rt6855_irq_lock);
++
++static void __iomem *rt_intc_membase;
++
++static inline void rt_intc_w32(u32 val, unsigned reg)
++{
++ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
++}
++
++static inline void rt_intc_prio_w8(u32 val, unsigned prio)
++{
++ __raw_writeb(val, rt_intc_membase + rt_intc_regs[INTC_REG_PRIO] + prio);
++}
++
++static inline u32 rt_intc_r32(unsigned reg)
++{
++ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
++}
++
++static void ralink_intc_irq_unmask(struct irq_data *d)
++{
++ unsigned long flags;
++ u32 mask;
++
++ spin_lock_irqsave(&rt6855_irq_lock, flags);
++
++ mask = rt_intc_r32(INTC_REG_MASK);
++ mask |= BIT(d->hwirq);
++ rt_intc_w32(mask, INTC_REG_MASK);
++
++ spin_unlock_irqrestore(&rt6855_irq_lock, flags);
++}
++
++static void ralink_intc_irq_mask(struct irq_data *d)
++{
++ unsigned long flags;
++ u32 mask;
++
++ spin_lock_irqsave(&rt6855_irq_lock, flags);
++
++ mask = rt_intc_r32(INTC_REG_MASK);
++ mask &= ~BIT(d->hwirq);
++ rt_intc_w32(mask, INTC_REG_MASK);
++
++ spin_unlock_irqrestore(&rt6855_irq_lock, flags);
++}
++
++static struct irq_chip ralink_intc_irq_chip = {
++ .name = "INTC",
++ .irq_ack = ralink_intc_irq_mask,
++ .irq_mask = ralink_intc_irq_mask,
++ .irq_mask_ack = ralink_intc_irq_mask,
++ .irq_unmask = ralink_intc_irq_unmask,
++ .irq_eoi = ralink_intc_irq_unmask,
++};
++
++unsigned int get_c0_compare_int(void)
++{
++ return RALINK_INTC_IRQ_BASE + RALINK_SOC_IRQ_TIMER;
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++ unsigned long pending;
++
++ pending = (read_c0_status() & read_c0_cause() & ST0_IM) >> 10;
++
++ do_IRQ(pending + RALINK_INTC_IRQ_BASE - 1);
++}
++
++static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t
hw)
++{
++ irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = intc_map,
++};
++
++static int __init intc_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ struct resource res;
++ struct irq_domain *domain;
++
++ if (!of_property_read_u32_array(node, "ralink,intc-registers",
++ rt_intc_regs, 2))
++ pr_info("intc: using register map from devicetree\n");
++
++ if (of_address_to_resource(node, 0, &res))
++ panic("Failed to get intc memory range");
++
++ if (!request_mem_region(res.start, resource_size(&res),
++ res.name))
++ pr_err("Failed to request intc memory");
++
++ rt_intc_membase = ioremap(res.start,
++ resource_size(&res));
++ if (!rt_intc_membase)
++ panic("Failed to remap intc memory");
++
++ rt_intc_prio_w8(RALINK_SOC_IRQ_TIMER, 4);
++ rt_intc_prio_w8(24, 3);
++ rt_intc_prio_w8(21, 2);
++ rt_intc_prio_w8(15, 1);
++
++ clear_c0_status(ST0_IM);
++ clear_c0_cause(CAUSEF_IP);
++
++ domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
++ RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add irqdomain");
++
++ set_c0_status(ST0_IM);
++
++ return 0;
++}
++
++static struct of_device_id __initdata of_irq_ids[] = {
++ { .compatible = "mti,cpu-interrupt-controller", .data =
mips_cpu_irq_of_init },
++ { .compatible = "ralink,rt6855a-intc", .data = intc_of_init },
++ {},
++};
++
++void __init arch_init_irq(void)
++{
++ of_irq_init(of_irq_ids);
++}
+diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
+index 8126f1260407..d0c7bd74505b 100644
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -22,6 +22,22 @@
+ #define RSTCTL_RESET_PCI BIT(26)
+ #define RSTCTL_RESET_SYSTEM BIT(0)
+
++#ifdef CONFIG_SOC_RT6855A
++#define CR_TIMER_BASE 0xBFBF0100
++#define CR_TIMER_CTL ((char*)(CR_TIMER_BASE + 0x00))
++#define CR_TIMER0_LDV (CR_TIMER_BASE + 0x04)
++
++#define SYS_HCLK (23333/100)
++
++#define TIMER_ENABLE 1
++#define TIMER_DISABLE 0
++#define TIMER_WDENABLE 1
++#define TIMER_WDDISABLE 0
++
++static const u8 rt6855a_timer_no = 5;
++
++#endif
++
+ static int ralink_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+ {
+@@ -91,6 +107,12 @@ static void ralink_restart(char *command)
+
+ local_irq_disable();
+ rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
++#ifdef CONFIG_SOC_RT6855A
++ writel((100 /* ms */ * SYS_HCLK) * 1000 / 2,
++ (char*)(CR_TIMER0_LDV+rt6855a_timer_no*0x08));
++ writel((TIMER_ENABLE << rt6855a_timer_no) | (TIMER_WDENABLE << 25),
++ CR_TIMER_CTL);
++#endif
+ unreachable();
+ }
+
+diff --git a/arch/mips/ralink/rt6855a.c b/arch/mips/ralink/rt6855a.c
+new file mode 100644
+index 000000000000..518a71a078cb
+--- /dev/null
++++ b/arch/mips/ralink/rt6855a.c
+@@ -0,0 +1,57 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2016 Imagination Technologies
++ * Author: Rafaël Carré <fun...@videolan.org>
++ */
++
++#include <linux/clk.h>
++#include <linux/clocksource.h>
++#include <linux/init.h>
++#include <linux/irqchip.h>
++#include <linux/of_clk.h>
++#include <linux/of_fdt.h>
++#include <linux/serial_reg.h>
++
++#include <asm/bootinfo.h>
++#include <asm/fw/fw.h>
++#include <asm/irq_cpu.h>
++#include <asm/machine.h>
++#include <asm/mips-cps.h>
++#include <asm/prom.h>
++#include <asm/smp-ops.h>
++#include <asm/time.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "common.h"
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++ soc_info->mem_size_min = 64;
++ soc_info->mem_size_max = 64;
++ soc_info->compatible = "ralink,rt6855a-soc";
++ soc_info->mem_base = 0x20000;
++ ralink_soc = RT6855A_SOC;
++}
++
++void __init ralink_of_remap(void)
++{
++ rt_sysc_membase = plat_of_remap_node("ralink,rt6855a-sysc");
++ rt_memc_membase = plat_of_remap_node("ralink,rt6855a-memc");
++
++ if (!rt_sysc_membase || !rt_memc_membase)
++ panic("Failed to remap core resources");
++}
++
++void __init ralink_clk_init(void)
++{
++ unsigned long sys_rate = 233333333;
++
++ /* TODO: move to DTS ? */
++
++ ralink_clk_add("cpu", 700000000);
++ ralink_clk_add("1fbf0100.watchdog", sys_rate);
++ ralink_clk_add("1fbf0000.uart", 40000000);
++ ralink_clk_add("1fb50000.ethernet", 700000000 / 2);
++ ralink_clk_add("1fbc0b00.spi", sys_rate);
++}
+--
+2.27.0
+
diff --git
a/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch
b/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch
new file mode 100644
index 0000000000..d8c8fd2122
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch
@@ -0,0 +1,35 @@
+From 6488e07a2f29f6dcd7e6531de7bc54cad920fc38 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org>
+Date: Wed, 23 Dec 2020 14:18:31 +0100
+Subject: [PATCH 2/4] HACK: spi-mt7621: rt6855a fix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+TODO: no idea what this does or if it's needed on other targets
+using this driver.
+
+Signed-off-by: Rafaël Carré <fun...@videolan.org>
+---
+ drivers/spi/spi-mt7621.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
+index 2c3b7a2a1ec7..58fb028ed776 100644
+--- a/drivers/spi/spi-mt7621.c
++++ b/drivers/spi/spi-mt7621.c
+@@ -87,7 +87,10 @@ static void mt7621_spi_set_cs(struct spi_device *spi, int
enable)
+ * reliably)
+ */
+ master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
+- master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
++ master |= MASTER_MORE_BUFMODE;
++#ifndef CONFIG_SOC_RT6855A
++ master |= MASTER_RS_SLAVE_SEL;
++#endif
+ master &= ~MASTER_FULL_DUPLEX;
+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
+
+--
+2.27.0
+
diff --git
a/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch
b/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch
new file mode 100644
index 0000000000..8eef843799
--- /dev/null
+++
b/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch
@@ -0,0 +1,69 @@
+From 5ebf28d61ae532fcbe1d852ae4e91d547025face Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org>
+Date: Wed, 23 Dec 2020 14:18:55 +0100
+Subject: [PATCH 3/4] HACK: spi-mt7621.c: hardcode frequency
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+TODO: use DTS
+
+Signed-off-by: Rafaël Carré <fun...@videolan.org>
+---
+ drivers/spi/spi-mt7621.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
+index 58fb028ed776..862303ec025b 100644
+--- a/drivers/spi/spi-mt7621.c
++++ b/drivers/spi/spi-mt7621.c
+@@ -341,7 +341,7 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+-
++#if 0
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
+@@ -352,7 +352,7 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ status = clk_prepare_enable(clk);
+ if (status)
+ return status;
+-
++#endif
+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
+ if (!master) {
+ dev_info(&pdev->dev, "master allocation failed\n");
+@@ -373,16 +373,16 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ rs->base = base;
+ rs->clk = clk;
+ rs->master = master;
+- rs->sys_freq = clk_get_rate(rs->clk);
++ rs->sys_freq = 233333333;//clk_get_rate(rs->clk);
+ rs->pending_write = 0;
+ dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
+
+- ret = device_reset(&pdev->dev);
++/* ret = device_reset(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "SPI reset failed!\n");
+ return ret;
+ }
+-
++*/
+ return devm_spi_register_controller(&pdev->dev, master);
+ }
+
+@@ -394,7 +394,7 @@ static int mt7621_spi_remove(struct platform_device *pdev)
+ master = dev_get_drvdata(&pdev->dev);
+ rs = spi_controller_get_devdata(master);
+
+- clk_disable_unprepare(rs->clk);
++// clk_disable_unprepare(rs->clk);
+
+ return 0;
+ }
+--
+2.27.0
+
diff --git
a/target/linux/ramips/patches-5.4/307-pci-rt3883-run-on-RT6855A.patch
b/target/linux/ramips/patches-5.4/307-pci-rt3883-run-on-RT6855A.patch
new file mode 100644
index 0000000000..b7d5e5e59b
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/307-pci-rt3883-run-on-RT6855A.patch
@@ -0,0 +1,271 @@
+From c66775b1d9df73c6fc96833f6b0556a3e756a1b8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org>
+Date: Wed, 23 Dec 2020 14:24:58 +0100
+Subject: [PATCH 4/4] pci-rt3883: run on RT6855A
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafaël Carré <fun...@videolan.org>
+---
+ arch/mips/boot/dts/ralink/rt6855.dtsi | 53 +++++++++------------------
+ arch/mips/boot/dts/ralink/wap300n.dts | 2 +-
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-rt3883.c | 42 ++++++++++++---------
+ 4 files changed, 45 insertions(+), 53 deletions(-)
+
+diff --git a/arch/mips/boot/dts/ralink/rt6855.dtsi
b/arch/mips/boot/dts/ralink/rt6855.dtsi
+index d083d1d1b984..76cd3da56834 100644
+--- a/arch/mips/boot/dts/ralink/rt6855.dtsi
++++ b/arch/mips/boot/dts/ralink/rt6855.dtsi
+@@ -109,13 +109,24 @@
+ };
+ };
+
+- pci: pci@1fb80000 {
++ pcie: pcie@1fb80000 {
+ compatible = "ralink,rt3883-pci";
+ reg = <0x1fb80000 0x20000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges; /* direct mapping */
++ #address-cells = <3>;
++ #size-cells = <2>;
+
++ #interrupt-cells = <1>;
++
++ device_type = "pci";
++ interrupt-map-mask = <0x0 0 0 0>;
++ interrupt-map = <0x0 0 0 0 &pciintc 20>;
++
++ ranges = <
++ 0x02000000 0 0x20000000 0x20000000 0 0x10000000 /* pci memory */
++ 0x01000000 0 0x1f600000 0x1f600000 0 0x00010000 /* io space */
++ >;
++
++ bus-range = <0 255>;
+ status = "disabled";
+
+ pciintc: interrupt-controller {
+@@ -123,35 +134,10 @@
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+
+- interrupt-parent = <&cpuintc>;
+- interrupts = <4>;
++ interrupt-parent = <&intc>;
++ interrupts = <24>;
+ };
+
+- pci@0 {
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+-
+- device_type = "pci";
+-
+- bus-range = <0 1>;
+- ranges = <
+- 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory
*/
+- 0x01000000 0 0x00000000 0x1f600000 0 0x00010000 /* io space */
+- >;
+-
+- pci0: pci@0 {
+- reg = <0x2000 0 0 0 0>;
+- device_type = "pci";
+- #address-cells = <3>;
+- #size-cells = <2>;
+-
+- status = "okay";
+-
+- bus-range = <0 1>;
+- ranges;
+- };
+- };
+ };
+
+ };
+@@ -196,12 +182,9 @@
+ };
+ };
+
+-&pci0 {
++&pcie {
+ wifi@0,0 {
+ compatible = "pci1814,3091";
+- reg = <0x0000 0 0 0 0>;
+- ralink,2ghz = <0>;
+ ralink,mtd-eeprom = <&factory 0x8000>;
+ };
+ };
+-
+diff --git a/arch/mips/boot/dts/ralink/wap300n.dts
b/arch/mips/boot/dts/ralink/wap300n.dts
+index e8f81578a589..7e8071b65c4e 100644
+--- a/arch/mips/boot/dts/ralink/wap300n.dts
++++ b/arch/mips/boot/dts/ralink/wap300n.dts
+@@ -16,7 +16,7 @@
+ bootargs = "console=ttyS0,57600";
+ };
+
+- pci@1fb80000 {
++ pcie@1fb80000 {
+ status = "okay";
+ };
+ };
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index d6de4cb2e31c..a197ffa93e35 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -51,6 +51,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
++obj-$(CONFIG_SOC_RT6855A) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
+index 0ac6346026d0..ef89da912012 100644
+--- a/arch/mips/pci/pci-rt3883.c
++++ b/arch/mips/pci/pci-rt3883.c
+@@ -38,7 +38,7 @@
+ #define RT3883_PCI_REG_IOBASE 0x2c
+ #define RT3883_PCI_REG_ARBCTL 0x80
+
+-#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
++#define RT3883_PCI_REG_BASE(_x) (0x2000 + (_x) * 0x1000)
+ #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
+ #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
+ #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
+@@ -53,7 +53,13 @@
+
+ #define RT3883_PCI_IRQ_COUNT 32
+
+-#define RT3883_P2P_BR_DEVNUM 1
++#ifdef CONFIG_SOC_RT6855A
++ #define RT3883_RSTCTRL_PCIE_SOC RT3883_RSTCTRL_PCIE_PCI_PDM;
++ #define RT3883_P2P_BR_DEVNUM 16
++#else
++ #define RT3883_RSTCTRL_PCIE_SOC RT3883_RSTCTRL_PCIE;
++ #define RT3883_P2P_BR_DEVNUM 1
++#endif
+
+ struct rt3883_pci_controller {
+ void __iomem *base;
+@@ -92,8 +98,7 @@ static inline void rt3883_pci_w32(struct
rt3883_pci_controller *rpc,
+ static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+ unsigned int func, unsigned int where)
+ {
+- return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+- 0x80000000;
++ return (bus << 24) | (slot << 19) | (func << 16) | (where & 0xfc);
+ }
+
+ static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
+@@ -235,7 +240,7 @@ static int rt3883_pci_config_read(struct pci_bus *bus,
unsigned int devfn,
+
+ rpc = pci_bus_to_rt3883_controller(bus);
+
+- if (!rpc->pcie_ready && bus->number == 1)
++ if (!rpc->pcie_ready && PCI_SLOT(devfn) == 1)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+@@ -269,7 +274,7 @@ static int rt3883_pci_config_write(struct pci_bus *bus,
unsigned int devfn,
+
+ rpc = pci_bus_to_rt3883_controller(bus);
+
+- if (!rpc->pcie_ready && bus->number == 1)
++ if (!rpc->pcie_ready && PCI_SLOT(devfn) == 1)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+@@ -314,7 +319,7 @@ static void rt3883_pci_preinit(struct
rt3883_pci_controller *rpc, unsigned mode)
+ clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
+
+ if (mode & RT3883_PCI_MODE_PCIE) {
+- rstctrl |= RT3883_RSTCTRL_PCIE;
++ rstctrl |= RT3883_RSTCTRL_PCIE_SOC;
+ rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
+
+ /* setup PCI PAD drive mode */
+@@ -355,7 +360,7 @@ static void rt3883_pci_preinit(struct
rt3883_pci_controller *rpc, unsigned mode)
+
+ if (mode & RT3883_PCI_MODE_PCIE) {
+ clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
+- rstctrl &= ~RT3883_RSTCTRL_PCIE;
++ rstctrl &= ~RT3883_RSTCTRL_PCIE_SOC;
+ }
+
+ rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
+@@ -385,9 +390,9 @@ static void rt3883_pci_preinit(struct
rt3883_pci_controller *rpc, unsigned mode)
+ if (!rpc->pcie_ready) {
+ /* reset the PCIe block */
+ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
+- t |= RT3883_RSTCTRL_PCIE;
++ t |= RT3883_RSTCTRL_PCIE_SOC;
+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
+- t &= ~RT3883_RSTCTRL_PCIE;
++ t &= ~RT3883_RSTCTRL_PCIE_SOC;
+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
+
+ /* turn off PCIe clock */
+@@ -449,14 +454,16 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ }
+
+ if (!rpc->pci_controller.of_node) {
+- dev_err(dev, "%pOF has no %s child node",
++ dev_info(dev, "%pOF has no %s child node",
+ rpc->intc_of_node,
+ "PCI host bridge");
+- err = -EINVAL;
+- goto err_put_intc_node;
++ rpc->pci_controller.of_node = np;
+ }
+
+ mode = RT3883_PCI_MODE_NONE;
++#ifdef CONFIG_SOC_RT6855A
++ mode = RT3883_PCI_MODE_PCIE;
++#else
+ for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
+ int devfn;
+
+@@ -478,6 +485,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ break;
+ }
+ }
++#endif
+
+ if (mode == RT3883_PCI_MODE_NONE) {
+ dev_err(dev, "unable to determine PCI mode\n");
+@@ -506,14 +514,14 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ ioport_resource.end = rpc->io_res.end;
+
+ /* PCI */
+- rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
++ rt3883_pci_w32(rpc, 0x7fff0000, RT3883_PCI_REG_BAR0SETUP(0));
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
+ rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
+
+ /* PCIe */
+- rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
++ rt3883_pci_w32(rpc, 0x7fff0000, RT3883_PCI_REG_BAR0SETUP(1));
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
+ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
+@@ -534,8 +542,8 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
+
+ if (mode == RT3883_PCI_MODE_PCIE) {
+- rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
+- rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
++ rt3883_pci_w32(rpc, 0x7fff0001, RT3883_PCI_REG_BAR0SETUP(0));
++ rt3883_pci_w32(rpc, 0x7fff0001, RT3883_PCI_REG_BAR0SETUP(1));
+
+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
+ PCI_BASE_ADDRESS_0,
+--
+2.27.0
+
--
2.27.0
_______________________________________________
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
