Thanks Harry.
Jeff Condit
----- Original Message -----
From: "Harry Selfridge" <[EMAIL PROTECTED]>
To: "Protel EDA Discussion List" <[email protected]>
Sent: Saturday, May 21, 2005 10:44 PM
Subject: Re: [PEDA] BGA Pad and Via sizes
Hi Jeff,
The new IPC-7351 guidelines say that for a copper defined land pattern,
the solder mask clearance should be a minimum of 0.075mm (0.00295in) from
the etched copper land. "For applications requiring a clearance that is
less than recommended, consult with the printed board supplier."
For solder mask defined patterns, "adjust the land pattern diameter
accordingly (see 14.4)." Section 14.4 talks about land pattern analysis
based on manufacturers data, and variations in the device.
There is a free land pattern viewer based on IPC-7351 available at the
following URL - it may give you some hints:
http://www.pcblibraries.com/resources/files/IPC-7351/IPC_Viewer_V3-000.zip
Regards - Harry
At 06:29 AM 5/14/2005, you wrote:
Hi all.
I'm using a Xilink FS48 package which has a 6x8 array of 0.40mm (+/-
0.05mm) solder balls on 0.80mm centers. I can't seem to find any
manufacturer's recommendations so I was going to default to a 0.32mm
copper defined pad. That's a factor of 0.8. If I went to a 0.300mm pad I
could get two 0.10mm traces between pads, but that is a factor of only
0.75 which seems too small. But then I got to thinking about the via
sizes and went searching the archives. I didn't really turn anything much
up so I thought I'd ask the group what they've found to be a good
combination for Pad, Pad mask, Via, Via Mask, Via Hole when using 0.40mm
solder balls on a 0.800mm pitch. Also, what are the IPC guidelines since
the latest revision for soldermask defined and copper defined?
Jeff Condit
snip
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