Thank you Brad,
Sincerely,
Rodrigo Giroto
Dpto Layout/Suporte Técnico
CADService Prod. Eletr. LTDA.
+55 (19)3246-1333
----- Original Message -----
From: "Brad Velander" <[EMAIL PROTECTED]>
To: "Protel EDA Discussion List" <[email protected]>
Sent: Wednesday, October 26, 2005 3:47 PM
Subject: RE: [PEDA] Error clearence fine pitch
Rodrigo,
Your problem could be handled in several manners, most would involve
creating "Classes" (See "D"esign, Classes) and incorporating them into your
clearance rules. You could make an additional spacing rule based upon
several possible classes.
i.e. Make a net class for the nets connecting to your fine pitch
component(s), use this class to write an additional spacing rule that allows
5 mil spacing for that net class.
Now that would allow 5 mil spacing for those nets anywhere that they went in
your design. You could get more restrictive and define other classes that
would allow or disallow that 5 mil spacing verses other classes of
nets/components/pads, etc..
Since the possible permutations could be endless, I hope that this helps and
gives you enough information to progress further with your rules definition.
Sincerely,
Brad Velander
Senior PCB Designer
Northern Airborne Technology
#14 - 1925 Kirschner Road,
Kelowna, BC, V1Y 4N7.
tel (250) 763-2329 ext. 225
fax (250) 762-3374
-----Original Message-----
From: Rodrigo Giroto [mailto:[EMAIL PROTECTED]
Sent: Wednesday, October 26, 2005 9:59 AM
To: [email protected]
Subject: [PEDA] Error clearence fine pitch
The general clearance design rule is 8 mils but my SMD fine pitched
components need a clearance of 5 mils. When I place tracks appears error of
clearence with pads. What to make?
Best Regards,
Rodrigo Giroto
Dpto Layout
CADService Prod. Eletr. LTDA.
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