Michael,
This is done in post processing when generating the Gerber files and the
check box 'Remove unconnected pads' is layer specific.
I apologize for not being more specific. I do not have Allegro in front
of me. So if you wish, you should be able to post to the Cadence
PCB_FORUM and/or the CDNUSERS forum. The PCB_FORUM is e-mail based.
The CDNUSERS forum is web based. Either one will let you search and or
register-to-post without having a maintenance contract or owning
Allegro.
Cadence PCB_FORUM;
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Cheers!
Drew
Andrew W. Riley III
Design Engineer
EADS North American Defense Test & Services
4 Goodyear
Irvine, CA 92618
(949) 460-2455
http://www.eads-nadefense.com/
[EMAIL PROTECTED]
-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Mira
Sent: Thursday, March 09, 2006 8:22 AM
To: Protel EDA Discussion List
Subject: Re: [PEDA] OT: Cadence thruhole question
Michael,
Can you be more specific? Do you mean Allegro or
Orcad?
Mira
--- "Robison, Michael R NAVSEA"
<[EMAIL PROTECTED]> wrote:
> I apologize for the off-topic post, but I haven't
> had any luck getting a response on
> the Cadence newsgroup. We use Protel for all our
> boards that we don't anticipate a
> need for signal-integrity analysis, but we've used
> Cadence on a 16-layer motherboard
> we are working.
>
> We need to turn off the annular ring generation on
> all thruholes on layers that have
> no electrical connection. With 7000 thruholes, we
> would like to not have to do it on
> a hole-by-hole basis. An off-list response would be
> appreciated.
>
> Thank you, Michael
>
>
>
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