Mira and Andrew,

Thank you for the coments.  I'm not sure if I've missed out on part of the 
thread
or what, but I'm not certain where the layer registration issues came into play.
We got our first cut in and we're fairly certain the copper is right, but the
board won't fly.  We designed it by relaying it out from legacy bitmap files of
the original layer artwork.  It was a tremendous undertaking.  We have a 
netlisting
tester here (something other than a DITMCO) that substantiated our copper path. 
 

But because copying old "pictures" of layers is an inexact science at best, we
now think that we allowed adjacent pads on internal layers that are bigger than 
on
the original, forcing twin traces closer together and thinner than what they are
on the original.  We are hoping that this combination is responsible for the 
prob-
lems we're experiencing, and that trimming down the unused pads and opening up 
the
area to wider and further apart traces will get us a product we can push out the
door.

Again, I really appreciate your help with our problems.

Thanks again,

Michael Robison
office   812-854-4953
cell     812-325-0820
Crane Naval Surface Warfare Center  

-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Behalf Of [EMAIL PROTECTED]
Sent: Friday, March 10, 2006 10:03
To: [email protected]
Subject: Re: [PEDA] OT: Cadence thruhole question


Mira, 

Just because I haven't had enough coffee this morning, did you mean
shortage, as in not enough ground plane, or did you mean electrical
shorts? 

Thanks,

aj

>-----Original Message-----
>From: [EMAIL PROTECTED] 
>[mailto:[EMAIL PROTECTED] On Behalf Of Mira
>Sent: Thursday, March 09, 2006 4:59 PM
>To: Protel EDA Discussion List
>Subject: Re: [PEDA] OT: Cadence thruhole question
>
>Hi Michael,
>
>...if your fab has problems with the layer 
>registration, you might end up with >>>shortages<<<
>in the power planes...


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