"Grump and complain as much as you like, I'll just keep cranking out paying designs using AD6."
Perhaps this is where some peoples view of the product begin to diverge. If you use it daily (therefore learning it's anomalies) and derive income from it's use, (therefore defraying it's costs), I can see how the anomalies might become less painful to you. I could afford the $2995 to buy Protel 3.x, and have upgraded all along the way to AD & SP4. I have done a few PCB designs for my previous employer, and a few for myself. But I do not use it daily, and I do not (at least directly) derive any income from it, at least at this point. The PCB I just finished, I used split plane feature, and found the autorouter connecting vias to the wrong split plane, connecting VCCO to VCCINT, placing VCCO vias on top of VCCINT vias (despite a via to via clearance rule) and failing to be able to complete 2 other traces, one of which a path for was completely obvious. I do not consider any of these problems to be insignificant. I ended up routing VCCO and VCCINT on the FPGA almost totally by hand, because it just simply could not do it. Situs was supposed to be a major cornerstone of the DXP release. I paid good money to upgrade to it. When I use it, I expect it to work. When it doesn't work at a basic functional level, I expect it to be fixed, and to get a version of it that does. I do not think I have got what I paid for. "Fool me once, shame on you. Fool me twice, shame on me." ---Phil ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
