On Wed, May 7, 2008 at 3:27 PM, Jie Jiang <[EMAIL PROTECTED]> wrote: > Hi Stephane, > > Have you solved this problem? > > Ps. Which version of perfmon/perfmn2 can support Intel X5300 series > processors, such as Xeon E5346? > > I am assuming this is a family 6 model 15 processor, right? Send me the content of /proc/cpuinfo.
> > > > However, there are two possible bugs: > > > > 1. The event definition of "SSE_PRE_MISS.STORES" in "core_event.h". > > > > This header file declares that the event SSE_PRE_MISS has a ucode of > > > > 0x03, which uname is STORE. However, according to Intel's latest > > > > Software Developer's Manual, Vol.3B, Appendix A.3, page A-19~A-20, > > > > there is no such event definition. I confirm this unit mask does not exists for the SSE_PRE_MISS event. I will remove it from libpfm. > > > > > > > > 2. When executing utisl/papi_native_avail, it reports the following > > > > errors in addtion to all native events available. > > > > > > > > I have traced this problem and found that it is caused by > > > > pfm_core_get_event_code() in Pfmlib_core.c. Actually, the macro > > > > definiton of MAX_COUNTERS is 4 in Pfmlib_core.c. > > > > That was indeed the problem. I have now fixed both issues in CVS. Please pull from CVS and tell me if this works for you now. Thanks for the bug reports. ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone _______________________________________________ perfmon2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
