> Hi Phil,
> 
> I see that there was code added to determine which registers are available.  
> Is 
> this code complete? When I run the kernel with the watchdog taking up pmc0, 
> things like papi's src/utils/papi_cost fails because pmc0 is unavailable. 
> Shouldn't the code be checking which pmcs are available before using them?

Hi Will,

I have no idea if the code is complete...the way PAPI works vs this
'unavailable' functionality is almost completely backwards. I added the
code to pfm_dispatch_events, but I guess it never makes it that far. The
problem is, I can't just decrement MAX_COUNTERS minus 1, because of the
darn disconnect between PMC's and PMD's on processors like the PIV. 

PAPI still thinks there are 4 registers on the AMD64 but just does
register allocation on 3. But I guess it never gets that far. If someone
can tell me how I should determine NUM_COUNTERS based on the number of
bits set in unavail_pmcs, maybe I could make this work. Stefane, is
there any code that can tell me, simply, how many PMD's I have left?

This is one reason I wish pfm could be integrated in some way to the
kernel. It should not tell me that num_counters is 4, nor that an event
can live on 4 counters, when in fact, the number is 3. PFM should hide
these details from me, or at least present a uniform view of what is
left of the PMU. When I call pfm_num_counters, I should get 3.

Anyways, it's likely that PAPI and Perfmon2 support will be broken for
quite a while given the upcoming changes to perfmon/libpfm, my lack of
hardware and everything I have to do for Supercomputing.

Thanks for helping with this.

Phil

> How is PAPI determining the register restrictions. On processors such as the 
> AMD64 all the perfmon registers can store the any of the events. For 
> processors 
> such as the Pentium IV there are) been verified to work?
> 
> Is papi add_native_events() going to have a problem when perfomon is being 
> used 
> with the watchdog? The number of available counters is going to be 
> MAX_COUNTERS-1.
> 
> -Will
> 
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