Hello Vince,
I have applied your patch though I have made some structural changes
to it. I think it is good to expose 2 new PMU models: Pentium II and Pentium
Pro.
This is what the patch does. The detection routines have been split due
to the logic inside libpfm.
I have tested this on my PIII. I don't have the older models, so I would
appreciate if you could try the attached patch.
If you need to use pfmon I have also attached the patch necessary to make
it aware of PPro and PII.
Thanks for your contributions.
On Tue, Oct 30, 2007 at 09:25:37PM -0400, Vince Weaver wrote:
>
> > Please re-send. I thought I had applied it at some point.
>
> Here is an updated version against the current tree.
>
>
> For Pentium Pro:
> A large number of PII/PIII only events removed.
>
> For Pentium II, the following were removed:
> EMON_KNI_PREF_DISPATCHED /* these are PIII only */
> EMON_KNI_PREF_MISS
> EMON_KNI_INST_RETIRED
> EMON_KNI_COMP_INST_RET
>
> For Pentium III, the following were removed:
> MMX_INSTR_EXEC /* the manual says these are PII only */
> MMX_INSTR_RET
>
> For Pentium M, the following were removed:
> MMX_INSTR_EXEC /* the manual says these are PII only */
> MMX_INSTR_RET
>
--
-Stephane
? lib/pfmlib_common.c.std
Index: include/perfmon/pfmlib.h
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/include/perfmon/pfmlib.h,v
retrieving revision 1.29
diff -u -p -r1.29 pfmlib.h
--- include/perfmon/pfmlib.h 15 Oct 2007 14:38:03 -0000 1.29
+++ include/perfmon/pfmlib.h 7 Nov 2007 23:47:32 -0000
@@ -197,12 +197,15 @@ extern int pfm_get_inst_retired_event(pf
#define PFMLIB_MONTECITO_PMU 4 /* Intel Dual-Core Itanium 2
9000 */
#define PFMLIB_AMD64_PMU 16 /* AMD AMD64 */
#define PFMLIB_GEN_IA32_PMU 63 /* Intel architectural PMU for
X86 */
-#define PFMLIB_I386_P6_PMU 32 /* Intel P6 (excl. Pentium M) */
+#define PFMLIB_I386_P6_PMU 32 /* Intel PIII (P6 core) */
#define PFMLIB_PENTIUM4_PMU 33 /* Intel Pentium4/Xeon/EM64T */
#define PFMLIB_COREDUO_PMU 34 /* Intel Core Duo/Core Solo */
#define PFMLIB_I386_PM_PMU 35 /* Intel Pentium M */
#define PFMLIB_CORE_PMU 36 /* obsolete, use
PFMLIB_INTEL_CORE_PMU */
#define PFMLIB_INTEL_CORE_PMU 36 /* Intel Core */
+#define PFMLIB_INTEL_PPRO_PMU 37 /* Intel Pentium Pro */
+#define PFMLIB_INTEL_PII_PMU 38 /* Intel Pentium II */
+
#define PFMLIB_MIPS_20KC_PMU 64 /* MIPS 20KC */
#define PFMLIB_MIPS_24K_PMU 65 /* MIPS 24K */
#define PFMLIB_MIPS_25KF_PMU 66 /* MIPS 25KF */
Index: include/perfmon/pfmlib_i386_p6.h
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/include/perfmon/pfmlib_i386_p6.h,v
retrieving revision 1.2
diff -u -p -r1.2 pfmlib_i386_p6.h
--- include/perfmon/pfmlib_i386_p6.h 23 Jul 2006 15:51:38 -0000 1.2
+++ include/perfmon/pfmlib_i386_p6.h 7 Nov 2007 23:47:32 -0000
@@ -1,7 +1,7 @@
/*
- * P6/Pentium M PMU specific types and definitions
+ * Intel Pentium II/Penttium PRO/Pentium III/Pentium M PMU specific types and
definitions
*
- * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <[EMAIL PROTECTED]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
Index: lib/i386_p6_events.h
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/lib/i386_p6_events.h,v
retrieving revision 1.4
diff -u -p -r1.4 i386_p6_events.h
--- lib/i386_p6_events.h 2 Feb 2007 09:02:19 -0000 1.4
+++ lib/i386_p6_events.h 7 Nov 2007 23:47:32 -0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <[EMAIL PROTECTED]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -77,6 +77,243 @@
}}
+#define I386_P6_PII_ONLY_PME \
+ {.pme_name = "MMX_INSTR_EXEC",\
+ .pme_code = 0xb0,\
+ .pme_desc = "Number of MMX instructions executed"\
+ },\
+ {.pme_name = "MMX_INSTR_RET",\
+ .pme_code = 0xce,\
+ .pme_desc = "Number of MMX instructions retired"\
+ }\
+
+#define I386_P6_PII_PIII_PME \
+ {.pme_name = "MMX_SAT_INSTR_EXEC",\
+ .pme_code = 0xb1,\
+ .pme_desc = "Number of MMX saturating instructions executed"\
+ },\
+ {.pme_name = "MMX_UOPS_EXEC",\
+ .pme_code = 0xb2,\
+ .pme_desc = "Number of MMX micro-ops executed"\
+ },\
+ {.pme_name = "MMX_INSTR_TYPE_EXEC",\
+ .pme_code = 0xb3,\
+ .pme_desc = "Number of MMX instructions executed by type",\
+ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
+ .pme_numasks = 6, \
+ .pme_umasks = { \
+ { .pme_uname = "MUL", \
+ .pme_udesc = "MMX packed multiply instructions executed", \
+ .pme_ucode = 0x1 \
+ }, \
+ { .pme_uname = "SHIFT", \
+ .pme_udesc = "MMX packed shift instructions executed", \
+ .pme_ucode = 0x2 \
+ }, \
+ { .pme_uname = "PACK", \
+ .pme_udesc = "MMX pack operation instructions executed", \
+ .pme_ucode = 0x4 \
+ }, \
+ { .pme_uname = "UNPACK", \
+ .pme_udesc = "MMX unpack operation instructions executed", \
+ .pme_ucode = 0x8 \
+ }, \
+ { .pme_uname = "LOGICAL", \
+ .pme_udesc = "MMX packed logical instructions executed", \
+ .pme_ucode = 0x10 \
+ }, \
+ { .pme_uname = "ARITH", \
+ .pme_udesc = "MMX packed arithmetic instructions executed", \
+ .pme_ucode = 0x20 \
+ } \
+ }\
+ },\
+ {.pme_name = "FP_MMX_TRANS",\
+ .pme_code = 0xcc,\
+ .pme_desc = "Number of MMX transitions",\
+ .pme_numasks = 2, \
+ .pme_umasks = { \
+ { .pme_uname = "TO_FP", \
+ .pme_udesc = "from MMX instructions to floating-point
instructions", \
+ .pme_ucode = 0x00 \
+ }, \
+ { .pme_uname = "TO_MMX", \
+ .pme_udesc = "from floating-point instructions to MMX
instructions", \
+ .pme_ucode = 0x01 \
+ }\
+ }\
+ },\
+ {.pme_name = "MMX_ASSIST",\
+ .pme_code = 0xcd,\
+ .pme_desc = "Number of MMX micro-ops executed"\
+ },\
+ {.pme_name = "SEG_RENAME_STALLS",\
+ .pme_code = 0xd4,\
+ .pme_desc = "Number of Segment Register Renaming Stalls", \
+ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
+ .pme_numasks = 4, \
+ .pme_umasks = { \
+ { .pme_uname = "ES", \
+ .pme_udesc = "Segment register ES", \
+ .pme_ucode = 0x1 \
+ }, \
+ { .pme_uname = "DS", \
+ .pme_udesc = "Segment register DS", \
+ .pme_ucode = 0x2 \
+ }, \
+ { .pme_uname = "FS", \
+ .pme_udesc = "Segment register FS", \
+ .pme_ucode = 0x4 \
+ }, \
+ { .pme_uname = "GS", \
+ .pme_udesc = "Segment register GS", \
+ .pme_ucode = 0x8 \
+ } \
+ }\
+ },\
+ {.pme_name = "SEG_REG_RENAMES",\
+ .pme_code = 0xd5,\
+ .pme_desc = "Number of Segment Register Renames", \
+ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
+ .pme_numasks = 4, \
+ .pme_umasks = { \
+ { .pme_uname = "ES", \
+ .pme_udesc = "Segment register ES", \
+ .pme_ucode = 0x1 \
+ }, \
+ { .pme_uname = "DS", \
+ .pme_udesc = "Segment register DS", \
+ .pme_ucode = 0x2 \
+ }, \
+ { .pme_uname = "FS", \
+ .pme_udesc = "Segment register FS", \
+ .pme_ucode = 0x4 \
+ }, \
+ { .pme_uname = "GS", \
+ .pme_udesc = "Segment register GS", \
+ .pme_ucode = 0x8 \
+ } \
+ }\
+ },\
+ {.pme_name = "RET_SEG_RENAMES",\
+ .pme_code = 0xd6,\
+ .pme_desc = "Number of segment register rename events retired"\
+ } \
+
+#define I386_P6_PIII_PME \
+ {.pme_name = "EMON_KNI_PREF_DISPATCHED",\
+ .pme_code = 0x07,\
+ .pme_desc = "Number of Streaming SIMD extensions
prefetch/weakly-ordered instructions dispatched " \
+ "(speculative prefetches are included in counting).
Pentium III and later",\
+ .pme_numasks = 4, \
+ .pme_umasks = { \
+ { .pme_uname = "NTA", \
+ .pme_udesc = "prefetch NTA", \
+ .pme_ucode = 0x00 \
+ }, \
+ { .pme_uname = "T1", \
+ .pme_udesc = "prefetch T1", \
+ .pme_ucode = 0x01 \
+ }, \
+ { .pme_uname = "T2", \
+ .pme_udesc = "prefetch T2", \
+ .pme_ucode = 0x02 \
+ }, \
+ { .pme_uname = "WEAK", \
+ .pme_udesc = "weakly ordered stores", \
+ .pme_ucode = 0x03 \
+ } \
+ } \
+ },\
+ {.pme_name = "EMON_KNI_PREF_MISS",\
+ .pme_code = 0x4b,\
+ .pme_desc = "Number of prefetch/weakly-ordered instructions that miss
all caches. Pentium III and later",\
+ .pme_numasks = 4, \
+ .pme_umasks = { \
+ { .pme_uname = "NTA", \
+ .pme_udesc = "prefetch NTA", \
+ .pme_ucode = 0x00 \
+ }, \
+ { .pme_uname = "T1", \
+ .pme_udesc = "prefetch T1", \
+ .pme_ucode = 0x01 \
+ }, \
+ { .pme_uname = "T2", \
+ .pme_udesc = "prefetch T2", \
+ .pme_ucode = 0x02 \
+ }, \
+ { .pme_uname = "WEAK", \
+ .pme_udesc = "weakly ordered stores", \
+ .pme_ucode = 0x03 \
+ } \
+ } \
+ } \
+
+
+#define I386_P6_CPU_CLK_UNHALTED \
+ {.pme_name = "CPU_CLK_UNHALTED",\
+ .pme_code = 0x79,\
+ .pme_desc = "Number cycles during which the processor is not halted"\
+ }\
+
+
+#define I386_P6_NOT_PM_PME \
+ {.pme_name = "L2_LD",\
+ .pme_code = 0x29,\
+ .pme_desc = "Number of L2 data loads. This event indicates that a
normal, unlocked, load memory access "\
+ "was received by the L2. It includes only L2 cacheable memory
accesses; it does not include I/O "\
+ "accesses, other non-memory accesses, or memory accesses such
as UC/WT memory accesses. It does include "\
+ "L2 cacheable TLB miss memory accesses",\
+ I386_P6_MESI_UMASKS\
+ },\
+ {.pme_name = "L2_LINES_IN",\
+ .pme_code = 0x24,\
+ .pme_desc = "Number of lines allocated in the L2"\
+ },\
+ {.pme_name = "L2_LINES_OUT",\
+ .pme_code = 0x26,\
+ .pme_desc = "Number of lines removed from the L2 for any reason"\
+ },\
+ {.pme_name = "L2_M_LINES_OUTM",\
+ .pme_code = 0x27,\
+ .pme_desc = "Number of modified lines removed from the L2 for any
reason"\
+ }\
+
+
+#define I386_P6_PIII_NOT_PM_PME \
+ {.pme_name = "EMON_KNI_INST_RETIRED",\
+ .pme_code = 0xd8,\
+ .pme_desc = "Number of SSE instructions retired. Pentium III and
later",\
+ .pme_numasks = 2, \
+ .pme_umasks = { \
+ { .pme_uname = "PACKED_SCALAR", \
+ .pme_udesc = "packed and scalar instructions", \
+ .pme_ucode = 0x00 \
+ }, \
+ { .pme_uname = "SCALAR", \
+ .pme_udesc = "scalar only", \
+ .pme_ucode = 0x01 \
+ } \
+ } \
+ },\
+ {.pme_name = "EMON_KNI_COMP_INST_RET",\
+ .pme_code = 0xd9,\
+ .pme_desc = "Number of SSE computation instructions retired. Pentium
III and later",\
+ .pme_numasks = 2, \
+ .pme_umasks = { \
+ { .pme_uname = "PACKED_SCALAR", \
+ .pme_udesc = "packed and scalar instructions", \
+ .pme_ucode = 0x00 \
+ }, \
+ { .pme_uname = "SCALAR", \
+ .pme_udesc = "scalar only", \
+ .pme_ucode = 0x01 \
+ } \
+ } \
+ }\
+
+
+
#define I386_P6_COMMON_PME \
{.pme_name = "INST_RETIRED",\
.pme_code = 0xc0,\
@@ -468,53 +705,6 @@
"Counting is performed if it is the first or second half
or if it is blocked, squashed, "\
"or missed. In this context, misaligned means crossing a
64-bit boundary"\
},\
- {.pme_name = "EMON_KNI_PREF_DISPATCHED",\
- .pme_code = 0x07,\
- .pme_desc = "Number of Streaming SIMD extensions
prefetch/weakly-ordered instructions dispatched " \
- "(speculative prefetches are included in counting).
Pentium III and later",\
- .pme_numasks = 4, \
- .pme_umasks = { \
- { .pme_uname = "NTA", \
- .pme_udesc = "prefetch NTA", \
- .pme_ucode = 0x00 \
- }, \
- { .pme_uname = "T1", \
- .pme_udesc = "prefetch T1", \
- .pme_ucode = 0x01 \
- }, \
- { .pme_uname = "T2", \
- .pme_udesc = "prefetch T2", \
- .pme_ucode = 0x02 \
- }, \
- { .pme_uname = "WEAK", \
- .pme_udesc = "weakly ordered stores", \
- .pme_ucode = 0x03 \
- } \
- } \
- },\
- {.pme_name = "EMON_KNI_PREF_MISS",\
- .pme_code = 0x4b,\
- .pme_desc = "Number of prefetch/weakly-ordered instructions that miss
all caches. Pentium III and later",\
- .pme_numasks = 4, \
- .pme_umasks = { \
- { .pme_uname = "NTA", \
- .pme_udesc = "prefetch NTA", \
- .pme_ucode = 0x00 \
- }, \
- { .pme_uname = "T1", \
- .pme_udesc = "prefetch T1", \
- .pme_ucode = 0x01 \
- }, \
- { .pme_uname = "T2", \
- .pme_udesc = "prefetch T2", \
- .pme_ucode = 0x02 \
- }, \
- { .pme_uname = "WEAK", \
- .pme_udesc = "weakly ordered stores", \
- .pme_ucode = 0x03 \
- } \
- } \
- },\
{.pme_name = "UOPS_RETIRED",\
.pme_code = 0xc2,\
.pme_desc = "Number of micro-ops retired"\
@@ -523,36 +713,6 @@
.pme_code = 0xd0,\
.pme_desc = "Number of instructions decoded"\
},\
- {.pme_name = "EMON_KNI_INST_RETIRED",\
- .pme_code = 0xd8,\
- .pme_desc = "Number of SSE instructions retired. Pentium III and
later",\
- .pme_numasks = 2, \
- .pme_umasks = { \
- { .pme_uname = "PACKED_SCALAR", \
- .pme_udesc = "packed and scalar instructions", \
- .pme_ucode = 0x00 \
- }, \
- { .pme_uname = "SCALAR", \
- .pme_udesc = "scalar only", \
- .pme_ucode = 0x01 \
- } \
- } \
- },\
- {.pme_name = "EMON_KNI_COMP_INST_RET",\
- .pme_code = 0xd9,\
- .pme_desc = "Number of SSE computation instructions retired. Pentium
III and later",\
- .pme_numasks = 2, \
- .pme_umasks = { \
- { .pme_uname = "PACKED_SCALAR", \
- .pme_udesc = "packed and scalar instructions", \
- .pme_ucode = 0x00 \
- }, \
- { .pme_uname = "SCALAR", \
- .pme_udesc = "scalar only", \
- .pme_ucode = 0x01 \
- } \
- } \
- },\
{.pme_name = "HW_INT_RX",\
.pme_code = 0xc8,\
.pme_desc = "Number of hardware interrupts received"\
@@ -615,160 +775,56 @@
{.pme_name = "SEGMENT_REG_LOADS",\
.pme_code = 0x06,\
.pme_desc = "Number of segment register loads."\
- },\
- {.pme_name = "MMX_INSTR_EXEC",\
- .pme_code = 0xb0,\
- .pme_desc = "Number of MMX instructions executed"\
- },\
- {.pme_name = "MMX_SAT_INSTR_EXEC",\
- .pme_code = 0xb1,\
- .pme_desc = "Number of MMX saturating instructions executed"\
- },\
- {.pme_name = "MMX_UOPS_EXEC",\
- .pme_code = 0xb2,\
- .pme_desc = "Number of MMX micro-ops executed"\
- },\
- {.pme_name = "MMX_INSTR_TYPE_EXEC",\
- .pme_code = 0xb3,\
- .pme_desc = "Number of MMX instructions executed by type",\
- .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
- .pme_numasks = 6, \
- .pme_umasks = { \
- { .pme_uname = "MUL", \
- .pme_udesc = "MMX packed multiply instructions executed", \
- .pme_ucode = 0x1 \
- }, \
- { .pme_uname = "SHIFT", \
- .pme_udesc = "MMX packed shift instructions executed", \
- .pme_ucode = 0x2 \
- }, \
- { .pme_uname = "PACK", \
- .pme_udesc = "MMX pack operation instructions executed", \
- .pme_ucode = 0x4 \
- }, \
- { .pme_uname = "UNPACK", \
- .pme_udesc = "MMX unpack operation instructions executed", \
- .pme_ucode = 0x8 \
- }, \
- { .pme_uname = "LOGICAL", \
- .pme_udesc = "MMX packed logical instructions executed", \
- .pme_ucode = 0x10 \
- }, \
- { .pme_uname = "ARITH", \
- .pme_udesc = "MMX packed arithmetic instructions executed", \
- .pme_ucode = 0x20 \
- } \
- }\
- },\
- {.pme_name = "FP_MMX_TRANS",\
- .pme_code = 0xcc,\
- .pme_desc = "Number of MMX transitions",\
- .pme_numasks = 2, \
- .pme_umasks = { \
- { .pme_uname = "TO_FP", \
- .pme_udesc = "from MMX instructions to floating-point
instructions", \
- .pme_ucode = 0x00 \
- }, \
- { .pme_uname = "TO_MMX", \
- .pme_udesc = "from floating-point instructions to MMX
instructions", \
- .pme_ucode = 0x01 \
- }\
- }\
- },\
- {.pme_name = "MMX_ASSIST",\
- .pme_code = 0xcd,\
- .pme_desc = "Number of MMX micro-ops executed"\
- },\
- {.pme_name = "MMX_INSTR_RET",\
- .pme_code = 0xce,\
- .pme_desc = "Number of MMX instructions retired"\
- },\
- {.pme_name = "SEG_RENAME_STALLS",\
- .pme_code = 0xd4,\
- .pme_desc = "Number of Segment Register Renaming Stalls", \
- .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
- .pme_numasks = 4, \
- .pme_umasks = { \
- { .pme_uname = "ES", \
- .pme_udesc = "Segment register ES", \
- .pme_ucode = 0x1 \
- }, \
- { .pme_uname = "DS", \
- .pme_udesc = "Segment register DS", \
- .pme_ucode = 0x2 \
- }, \
- { .pme_uname = "FS", \
- .pme_udesc = "Segment register FS", \
- .pme_ucode = 0x4 \
- }, \
- { .pme_uname = "GS", \
- .pme_udesc = "Segment register GS", \
- .pme_ucode = 0x8 \
- } \
- }\
- },\
- {.pme_name = "SEG_REG_RENAMES",\
- .pme_code = 0xd5,\
- .pme_desc = "Number of Segment Register Renames", \
- .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \
- .pme_numasks = 4, \
- .pme_umasks = { \
- { .pme_uname = "ES", \
- .pme_udesc = "Segment register ES", \
- .pme_ucode = 0x1 \
- }, \
- { .pme_uname = "DS", \
- .pme_udesc = "Segment register DS", \
- .pme_ucode = 0x2 \
- }, \
- { .pme_uname = "FS", \
- .pme_udesc = "Segment register FS", \
- .pme_ucode = 0x4 \
- }, \
- { .pme_uname = "GS", \
- .pme_udesc = "Segment register GS", \
- .pme_ucode = 0x8 \
- } \
- }\
- },\
- {.pme_name = "RET_SEG_RENAMES",\
- .pme_code = 0xd6,\
- .pme_desc = "Number of segment register rename events retired"\
- }
+ }\
+
+
/*
- * Generic P6 processor event table
+ * Pentium Pro Processor Event Table
*/
-static pme_i386_p6_entry_t i386_p6_pe []={
- {.pme_name = "CPU_CLK_UNHALTED",
- .pme_code = 0x79,
- .pme_desc = "Number cycles during which the processor is not halted"
- },
- I386_P6_COMMON_PME,
- {.pme_name = "L2_LD",
- .pme_code = 0x29,
- .pme_desc = "Number of L2 data loads. This event indicates that a
normal, unlocked, load memory access "
- "was received by the L2. It includes only L2 cacheable memory
accesses; it does not include I/O "
- "accesses, other non-memory accesses, or memory accesses such
as UC/WT memory accesses. It does include "
- "L2 cacheable TLB miss memory accesses",
- I386_P6_MESI_UMASKS
- },
- {.pme_name = "L2_LINES_IN",
- .pme_code = 0x24,
- .pme_desc = "Number of lines allocated in the L2"
- },
- {.pme_name = "L2_LINES_OUT",
- .pme_code = 0x26,
- .pme_desc = "Number of lines removed from the L2 for any reason"
- },
- {.pme_name = "L2_M_LINES_OUTM",
- .pme_code = 0x27,
- .pme_desc = "Number of modified lines removed from the L2 for any
reason"
- }
+static pme_i386_p6_entry_t i386_ppro_pe []={
+ I386_P6_CPU_CLK_UNHALTED, /* should be first */
+ I386_P6_COMMON_PME, /* generic p6 */
+ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */
+};
+
+#define PME_I386_PPRO_CPU_CLK_UNHALTED 0
+#define PME_I386_PPRO_INST_RETIRED 1
+#define PME_I386_PPRO_EVENT_COUNT
(sizeof(i386_ppro_pe)/sizeof(pme_i386_p6_entry_t))
+
+
+/*
+ * Pentium II Processor Event Table
+ */
+static pme_i386_p6_entry_t i386_pII_pe []={
+ I386_P6_CPU_CLK_UNHALTED, /* should be first */
+ I386_P6_COMMON_PME, /* generic p6 */
+ I386_P6_PII_ONLY_PME, /* pentium II only */
+ I386_P6_PII_PIII_PME, /* pentium II and later */
+ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */
};
-#define PME_I386_P6_CPU_CLK_UNHALTED 0
-#define PME_I386_P6_INST_RETIRED 1
-#define PME_I386_P6_EVENT_COUNT
(sizeof(i386_p6_pe)/sizeof(pme_i386_p6_entry_t))
+
+#define PME_I386_PII_CPU_CLK_UNHALTED 0
+#define PME_I386_PII_INST_RETIRED 1
+#define PME_I386_PII_EVENT_COUNT
(sizeof(i386_pII_pe)/sizeof(pme_i386_p6_entry_t))
+
+
+/*
+ * Pentium III Processor Event Table
+ */
+static pme_i386_p6_entry_t i386_pIII_pe []={
+ I386_P6_CPU_CLK_UNHALTED, /* should be first */
+ I386_P6_COMMON_PME, /* generic p6 */
+ I386_P6_PII_PIII_PME, /* pentium II and later */
+ I386_P6_PIII_PME, /* pentium III and later */
+ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */
+ I386_P6_PIII_NOT_PM_PME /* pentium III that conflict with Pentium M */
+};
+
+#define PME_I386_PIII_CPU_CLK_UNHALTED 0
+#define PME_I386_PIII_INST_RETIRED 1
+#define PME_I386_PIII_EVENT_COUNT
(sizeof(i386_pIII_pe)/sizeof(pme_i386_p6_entry_t))
+
/*
* Pentium M event table
@@ -783,7 +839,9 @@ static pme_i386_p6_entry_t i386_pm_pe []
.pme_desc = "Number cycles during which the processor is not halted
and not in a thermal trip"
},
- I386_P6_COMMON_PME,
+ I386_P6_COMMON_PME, /* generic p6 */
+ I386_P6_PII_PIII_PME, /* pentium II and later */
+ I386_P6_PIII_PME, /* pentium III and later */
{.pme_name = "EMON_EST_TRANS",
.pme_code = 0x58,
Index: lib/pfmlib_common.c
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/lib/pfmlib_common.c,v
retrieving revision 1.34
diff -u -p -r1.34 pfmlib_common.c
--- lib/pfmlib_common.c 3 Nov 2007 12:29:03 -0000 1.34
+++ lib/pfmlib_common.c 7 Nov 2007 23:47:32 -0000
@@ -52,6 +52,8 @@ static pfm_pmu_support_t *supported_pmus
#endif
#ifdef CONFIG_PFMLIB_ARCH_I386
+ &i386_pii_support,
+ &i386_ppro_support,
&i386_p6_support,
&i386_pm_support,
&coreduo_support,
Index: lib/pfmlib_i386_p6.c
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/lib/pfmlib_i386_p6.c,v
retrieving revision 1.22
diff -u -p -r1.22 pfmlib_i386_p6.c
--- lib/pfmlib_i386_p6.c 25 Oct 2007 15:24:15 -0000 1.22
+++ lib/pfmlib_i386_p6.c 7 Nov 2007 23:47:32 -0000
@@ -2,7 +2,7 @@
* pfmlib_i386_pm.c : support for the P6 processor family (family=6)
* incl. Pentium II, Pentium III, Pentium Pro, Pentium M
*
- * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P.
* Contributed by Stephane Eranian <[EMAIL PROTECTED]>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -33,7 +33,7 @@
/* private headers */
#include "pfmlib_priv.h" /* library private */
#include "pfmlib_i386_p6_priv.h" /* architecture private */
-#include "i386_p6_events.h" /* event tables P6 and Pentium
M */
+#include "i386_p6_events.h" /* event tables */
/* let's define some handy shortcuts! */
#define sel_event_mask perfsel.sel_event_mask
@@ -49,7 +49,7 @@
static char * pfm_i386_p6_get_event_name(unsigned int i);
static pme_i386_p6_entry_t *i386_pe;
-static unsigned int i386_p6_num_events;
+static int i386_p6_cycle_event, i386_p6_inst_retired_event;
#define PFMLIB_I386_P6_HAS_COMBO(_e) ((i386_pe[_e].pme_flags &
PFMLIB_I386_P6_UMASK_COMBO) != 0)
@@ -91,12 +91,39 @@ pfm_i386_detect_common(void)
return family != 6 ? PFMLIB_ERR_NOTSUPP : PFMLIB_SUCCESS;
}
+/*
+ * detect Pentium Pro
+ */
+static int
+pfm_i386_p6_detect_ppro(void)
+{
+ int ret, model;
+ char buffer[128];
+
+ ret = pfm_i386_detect_common();
+ if (ret != PFMLIB_SUCCESS)
+ return ret;
+
+ ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer));
+ if (ret == -1)
+ return PFMLIB_ERR_NOTSUPP;
+
+ model = atoi(buffer);
+
+ if (model != 1)
+ return PFMLIB_ERR_NOTSUPP;
+
+ i386_pe = i386_ppro_pe;
+ i386_p6_cycle_event = PME_I386_PPRO_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PPRO_INST_RETIRED;
+ return PFMLIB_SUCCESS;
+}
/*
- * detect non Pentium M P6 cores
+ * detect Pentium II
*/
static int
-pfm_i386_p6_detect(void)
+pfm_i386_p6_detect_pii(void)
{
int ret, model;
char buffer[128];
@@ -112,28 +139,59 @@ pfm_i386_p6_detect(void)
model = atoi(buffer);
switch(model) {
- case 1: /* Pentium Pro */
case 3: /* Pentium II */
case 5: /* Pentium II Deschutes */
+ case 6: /* Pentium II Mendocino */
+ i386_pe = i386_pII_pe;
+ i386_p6_cycle_event = PME_I386_PII_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PII_INST_RETIRED;
+ break;
+ default:
+ return PFMLIB_ERR_NOTSUPP;
+ }
+ return PFMLIB_SUCCESS;
+}
+
+/*
+ * detect Pentium III
+ */
+static int
+pfm_i386_p6_detect_piii(void)
+{
+ int ret, model;
+ char buffer[128];
+
+ ret = pfm_i386_detect_common();
+ if (ret != PFMLIB_SUCCESS)
+ return ret;
+
+ ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer));
+ if (ret == -1)
+ return PFMLIB_ERR_NOTSUPP;
+
+ model = atoi(buffer);
+
+ switch(model) {
case 7: /* Pentium III Katmai */
case 8: /* Pentium III Coppermine */
case 9: /* Mobile Pentium III */
case 10:/* Pentium III Cascades */
case 11:/* Pentium III Tualatin */
+ i386_pe = i386_pIII_pe;
+ i386_p6_cycle_event = PME_I386_PIII_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PIII_INST_RETIRED;
break;
default:
return PFMLIB_ERR_NOTSUPP;
}
- i386_pe = i386_p6_pe;
- i386_p6_num_events = PME_I386_P6_EVENT_COUNT;
return PFMLIB_SUCCESS;
}
/*
- * detect only Pentium M core
+ * detect Pentium M
*/
static int
-pfm_i386_pm_detect(void)
+pfm_i386_p6_detect_pm(void)
{
int ret, model;
char buffer[128];
@@ -151,7 +209,8 @@ pfm_i386_pm_detect(void)
return PFMLIB_ERR_NOTSUPP;
i386_pe = i386_pm_pe;
- i386_p6_num_events = PME_I386_PM_EVENT_COUNT;
+ i386_p6_cycle_event = PME_I386_PM_CPU_CLK_UNHALTED;
+ i386_p6_inst_retired_event = PME_I386_PM_INST_RETIRED;
return PFMLIB_SUCCESS;
}
@@ -457,7 +516,7 @@ pfm_i386_p6_get_event_mask_code(unsigned
static int
pfm_i386_p6_get_cycle_event(pfmlib_event_t *e)
{
- e->event = PME_I386_P6_CPU_CLK_UNHALTED;
+ e->event = i386_p6_cycle_event;
return PFMLIB_SUCCESS;
}
@@ -465,30 +524,65 @@ pfm_i386_p6_get_cycle_event(pfmlib_event
static int
pfm_i386_p6_get_inst_retired(pfmlib_event_t *e)
{
- e->event = PME_I386_P6_INST_RETIRED;
- return PFMLIB_SUCCESS;
-}
-
-static int
-pfm_i386_pm_get_cycle_event(pfmlib_event_t *e)
-{
- e->event = PME_I386_PM_CPU_CLK_UNHALTED;
- return PFMLIB_SUCCESS;
-
-}
-
-static int
-pfm_i386_pm_get_inst_retired(pfmlib_event_t *e)
-{
- e->event = PME_I386_PM_INST_RETIRED;
+ e->event = i386_p6_inst_retired_event;
return PFMLIB_SUCCESS;
}
+/* Pentium II support */
+pfm_pmu_support_t i386_pii_support={
+ .pmu_name = "Intel Pentium II",
+ .pmu_type = PFMLIB_INTEL_PII_PMU,
+ .pme_count = PME_I386_PII_EVENT_COUNT,
+ .pmc_count = PMU_I386_P6_NUM_PERFSEL,
+ .pmd_count = PMU_I386_P6_NUM_PERFCTR,
+ .num_cnt = PMU_I386_P6_NUM_COUNTERS,
+ .get_event_code = pfm_i386_p6_get_event_code,
+ .get_event_name = pfm_i386_p6_get_event_name,
+ .get_event_counters = pfm_i386_p6_get_event_counters,
+ .dispatch_events = pfm_i386_p6_dispatch_events,
+ .pmu_detect = pfm_i386_p6_detect_pii,
+ .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
+ .get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
+ .get_impl_counters = pfm_i386_p6_get_impl_counters,
+ .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width,
+ .get_event_desc = pfm_i386_p6_get_event_description,
+ .get_num_event_masks = pfm_i386_p6_get_num_event_masks,
+ .get_event_mask_name = pfm_i386_p6_get_event_mask_name,
+ .get_event_mask_code = pfm_i386_p6_get_event_mask_code,
+ .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc,
+ .get_cycle_event = pfm_i386_p6_get_cycle_event,
+ .get_inst_retired_event = pfm_i386_p6_get_inst_retired
+};
/* Generic P6 processor support (not incl. Pentium M) */
pfm_pmu_support_t i386_p6_support={
.pmu_name = "Intel P6 Processor Family",
.pmu_type = PFMLIB_I386_P6_PMU,
- .pme_count = PME_I386_P6_EVENT_COUNT,
+ .pme_count = PME_I386_PIII_EVENT_COUNT,
+ .pmc_count = PMU_I386_P6_NUM_PERFSEL,
+ .pmd_count = PMU_I386_P6_NUM_PERFCTR,
+ .num_cnt = PMU_I386_P6_NUM_COUNTERS,
+ .get_event_code = pfm_i386_p6_get_event_code,
+ .get_event_name = pfm_i386_p6_get_event_name,
+ .get_event_counters = pfm_i386_p6_get_event_counters,
+ .dispatch_events = pfm_i386_p6_dispatch_events,
+ .pmu_detect = pfm_i386_p6_detect_piii,
+ .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
+ .get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
+ .get_impl_counters = pfm_i386_p6_get_impl_counters,
+ .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width,
+ .get_event_desc = pfm_i386_p6_get_event_description,
+ .get_num_event_masks = pfm_i386_p6_get_num_event_masks,
+ .get_event_mask_name = pfm_i386_p6_get_event_mask_name,
+ .get_event_mask_code = pfm_i386_p6_get_event_mask_code,
+ .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc,
+ .get_cycle_event = pfm_i386_p6_get_cycle_event,
+ .get_inst_retired_event = pfm_i386_p6_get_inst_retired
+};
+
+pfm_pmu_support_t i386_ppro_support={
+ .pmu_name = "Intel Pentium Pro",
+ .pmu_type = PFMLIB_INTEL_PPRO_PMU,
+ .pme_count = PME_I386_PPRO_EVENT_COUNT,
.pmc_count = PMU_I386_P6_NUM_PERFSEL,
.pmd_count = PMU_I386_P6_NUM_PERFCTR,
.num_cnt = PMU_I386_P6_NUM_COUNTERS,
@@ -496,7 +590,7 @@ pfm_pmu_support_t i386_p6_support={
.get_event_name = pfm_i386_p6_get_event_name,
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
- .pmu_detect = pfm_i386_p6_detect,
+ .pmu_detect = pfm_i386_p6_detect_ppro,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
@@ -510,6 +604,7 @@ pfm_pmu_support_t i386_p6_support={
.get_inst_retired_event = pfm_i386_p6_get_inst_retired
};
+
/* Pentium M support */
pfm_pmu_support_t i386_pm_support={
.pmu_name = "Intel Pentium M",
@@ -522,7 +617,7 @@ pfm_pmu_support_t i386_pm_support={
.get_event_name = pfm_i386_p6_get_event_name,
.get_event_counters = pfm_i386_p6_get_event_counters,
.dispatch_events = pfm_i386_p6_dispatch_events,
- .pmu_detect = pfm_i386_pm_detect,
+ .pmu_detect = pfm_i386_p6_detect_pm,
.get_impl_pmcs = pfm_i386_p6_get_impl_perfsel,
.get_impl_pmds = pfm_i386_p6_get_impl_perfctr,
.get_impl_counters = pfm_i386_p6_get_impl_counters,
@@ -532,6 +627,6 @@ pfm_pmu_support_t i386_pm_support={
.get_event_mask_name = pfm_i386_p6_get_event_mask_name,
.get_event_mask_code = pfm_i386_p6_get_event_mask_code,
.get_event_mask_desc = pfm_i386_p6_get_event_mask_desc,
- .get_cycle_event = pfm_i386_pm_get_cycle_event,
- .get_inst_retired_event = pfm_i386_pm_get_inst_retired
+ .get_cycle_event = pfm_i386_p6_get_cycle_event,
+ .get_inst_retired_event = pfm_i386_p6_get_inst_retired
};
Index: lib/pfmlib_priv.h
===================================================================
RCS file: /cvsroot/perfmon2/libpfm/lib/pfmlib_priv.h,v
retrieving revision 1.17
diff -u -p -r1.17 pfmlib_priv.h
--- lib/pfmlib_priv.h 15 Oct 2007 14:38:03 -0000 1.17
+++ lib/pfmlib_priv.h 7 Nov 2007 23:47:32 -0000
@@ -98,6 +98,8 @@ extern pfm_pmu_support_t itanium_support
extern pfm_pmu_support_t generic_ia64_support;
extern pfm_pmu_support_t amd64_support;
extern pfm_pmu_support_t i386_p6_support;
+extern pfm_pmu_support_t i386_ppro_support;
+extern pfm_pmu_support_t i386_pii_support;
extern pfm_pmu_support_t i386_pm_support;
extern pfm_pmu_support_t gen_ia32_support;
extern pfm_pmu_support_t generic_mips64_support;
? pfmon/pfmon
? pfmon/smpl_mod/pebs_hist_smpl.c
? pfmon/smpl_mod/pebs_smpl_simple.c
Index: pfmon/pfmon.c
===================================================================
RCS file: /cvsroot/perfmon2/pfmon/pfmon/pfmon.c,v
retrieving revision 1.46
diff -u -p -r1.46 pfmon.c
--- pfmon/pfmon.c 18 Oct 2007 14:49:56 -0000 1.46
+++ pfmon/pfmon.c 7 Nov 2007 23:47:48 -0000
@@ -47,6 +47,8 @@ static pfmon_support_t *pfmon_cpus[]={
&pfmon_pentium4,
&pfmon_core,
&pfmon_i386_p6,
+ &pfmon_i386_pii,
+ &pfmon_i386_ppro,
&pfmon_i386_pm,
&pfmon_coreduo,
&pfmon_gen_ia32, /* must always be last of X86 choices */
Index: pfmon/pfmon_i386_p6.c
===================================================================
RCS file: /cvsroot/perfmon2/pfmon/pfmon/pfmon_i386_p6.c,v
retrieving revision 1.11
diff -u -p -r1.11 pfmon_i386_p6.c
--- pfmon/pfmon_i386_p6.c 3 Nov 2007 13:28:18 -0000 1.11
+++ pfmon/pfmon_i386_p6.c 7 Nov 2007 23:47:48 -0000
@@ -355,6 +355,41 @@ pfmon_i386_p6_verify_cmdline(int argc, c
if (options.opt_data_trigger_ro)
fatal_error("the --trigger-data-ro option is not supported by
this processor\n");
}
+/* Pentium II */
+pfmon_support_t pfmon_i386_pii={
+ .name = "Intel Pentium II",
+ .pmu_type = PFMLIB_INTEL_PII_PMU,
+ .generic_pmu_type = PFMLIB_NO_PMU,
+ .pfmon_initialize = pfmon_i386_p6_initialize,
+ .pfmon_usage = pfmon_i386_p6_usage,
+ .pfmon_parse_options = pfmon_i386_p6_parse_options,
+ .pfmon_create_set = pfmon_i386_p6_create_set,
+ .pfmon_setup = pfmon_i386_p6_setup,
+ .pfmon_prepare_registers = pfmon_i386_p6_prepare_registers,
+ .pfmon_install_pmc_registers = pfmon_i386_p6_install_pmc_registers,
+ .pfmon_install_pmd_registers = pfmon_i386_p6_install_pmd_registers,
+ .pfmon_print_header = pfmon_i386_p6_print_header,
+ .pfmon_setup_ctx_flags = pfmon_i386_p6_setup_ctx_flags,
+ .pfmon_verify_cmdline = pfmon_i386_p6_verify_cmdline,
+};
+
+/* Pentium Pro */
+pfmon_support_t pfmon_i386_ppro={
+ .name = "Intel Pentium Pro",
+ .pmu_type = PFMLIB_INTEL_PPRO_PMU,
+ .generic_pmu_type = PFMLIB_NO_PMU,
+ .pfmon_initialize = pfmon_i386_p6_initialize,
+ .pfmon_usage = pfmon_i386_p6_usage,
+ .pfmon_parse_options = pfmon_i386_p6_parse_options,
+ .pfmon_create_set = pfmon_i386_p6_create_set,
+ .pfmon_setup = pfmon_i386_p6_setup,
+ .pfmon_prepare_registers = pfmon_i386_p6_prepare_registers,
+ .pfmon_install_pmc_registers = pfmon_i386_p6_install_pmc_registers,
+ .pfmon_install_pmd_registers = pfmon_i386_p6_install_pmd_registers,
+ .pfmon_print_header = pfmon_i386_p6_print_header,
+ .pfmon_setup_ctx_flags = pfmon_i386_p6_setup_ctx_flags,
+ .pfmon_verify_cmdline = pfmon_i386_p6_verify_cmdline,
+};
pfmon_support_t pfmon_i386_p6={
.name = "Intel P6 processor",
Index: pfmon/pfmon_support.h
===================================================================
RCS file: /cvsroot/perfmon2/pfmon/pfmon/pfmon_support.h,v
retrieving revision 1.4
diff -u -p -r1.4 pfmon_support.h
--- pfmon/pfmon_support.h 3 Oct 2007 09:00:02 -0000 1.4
+++ pfmon/pfmon_support.h 7 Nov 2007 23:47:48 -0000
@@ -33,6 +33,8 @@ extern pfmon_support_t pfmon_montecito;
extern pfmon_support_t pfmon_generic_ia64;
extern pfmon_support_t pfmon_amd64;
extern pfmon_support_t pfmon_i386_pm;
+extern pfmon_support_t pfmon_i386_pii;
+extern pfmon_support_t pfmon_i386_ppro;
extern pfmon_support_t pfmon_i386_p6;
extern pfmon_support_t pfmon_pentium4;
extern pfmon_support_t pfmon_gen_ia32;
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