On Thursday 14 November 2002 10:32, Leopold Toetsch wrote: > Daniel Grunblatt wrote: > > On Thursday 14 November 2002 05:14, Leopold Toetsch wrote: > >>What JIT needs to know is the location of the resume opcode, to mark it > >>as a jump target properly, so that processor registers can be setup > >>correctly. > > > > Well, any opcode could be a target, so I suggest to build something like > > a section entrance code that given the PC could load the apropiate > > registers and jump to the middle of a jitted section. Yes, it will be > > slow but we are talking about exceptions here. > > There must be some code, that installs the exception handler. This code > has the address of the exception handler, which JIT has to know too. > Being prepared to enter at arbitrary places in JIT would inhibit > processor register usage totally, or wouldn't be any win. >
Either I didn't make my self clear (sorry) or my understanding of exceptions is wrong ... probably both. When, say, div throws an exception it will longjmp to the handler, that handler will know where to continue the execution of the program, right? so after doing its job it will have to call a function that given a PC will load the cpu registers as needed and jump into the jitted code again but if there was no exception the jitted code executes as usual. > >>So we IMHO need to mark each OP with a flag, if it might throw an > >>exception and restore all processor registers to parrot registers before > >>doing this OP. > > > > Since there isn't any jitted opcode throwing an exception ... > > div by zero, modulo (div currently only PPC but...) > > > (and all registers > > are saved back to parrot register before calling C code), > > ... which I want to avoid for callee saved registers ... > > > and if there were > > any opcode jitted throwing an exception it must save the registers back > > before doing so. > > So, it would be useful to know, which op code might throw an exception. Certainly. > > > Daniel Grunblatt. > > leo Daniel Grunblatt.
