Gavin Sherry <[EMAIL PROTECTED]> writes: > What about padding the LWLock to 64 bytes on these architectures. Both P4 > and Opteron have 64 byte cache lines, IIRC. This would ensure that a > cacheline doesn't hold two LWLocks.
I tried that first, actually, but it was a net loss. I guess enlarging
the array that much wastes too much cache space.
regards, tom lane
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TIP 2: Don't 'kill -9' the postmaster
