Weekly ping. Tarball re-attached for your convenience.
While there, I changed the master site from Github to
opencircuitdesign.com (so we can avoid the on-the-fly generated
archive).
If you would like to play a bit with the port:
- make a new directory (e.g. ./qflow-trial) and copy there the enclosed
map9v3.v file;
- change to that dir and run 'qflow gui';
- in the 'synthesys preparation' tab:
* select map9v3.v as Verilog source file;
* the 'Verilog module' field will be updated automatically;
* click on 'Set stop' after every synthesis step;
- click on 'Run' in the 'Preparation' row;
- then run the other steps in sequence;
- starting after the 'Placement', you'll be able to see the layout
clicking on 'Edit Layout' (type 'v' in Magic window to see the full
view).
On 21/06/2020 16:40, Tim Edwards wrote:
Hello Alessandro,OSU 050/035/018 tech files have a proprietary license that says: [...] "Permission to use, copy, and modify this software and its documentation for research and educational purposes only and without fee or royalty is hereby granted..." [...] I don't know if this is too restrictive; if so, we should probably split the package; please let me know how to proceed;This should not be a problem. The technologies are based on the MOSIS SCMOS technologies (see www.mosis.com). Specifically, the process technology file for Magic is designed to be submitted to MOSIS for use with the TSMC foundry. However, as of about two years ago, MOSIS stopped supporting the SCMOS technology description for TSMC. Therefore, designs using these cells are, for all intents and purposes, purely educational, as there is no way to fabricate such a design. Regards, Tim +--------------------------------+-------------------------------------+ | R. Timothy Edwards (Tim) | email: t...@opencircuitdesign.com | | Open Circuit Design | web: http://opencircuitdesign.com | | 19601 Jerusalem Road | phone: (240) 489-3255 | | Poolesville, MD 20837 | cell: (408) 828-8212 | +--------------------------------+-------------------------------------+
-- Alessandro De Laurenzis [mailto:jus...@atlantide.mooo.com] Web: http://www.atlantide.mooo.com LinkedIn: http://it.linkedin.com/in/delaurenzis
qflow-1.4.83.tar.gz
Description: application/gzip
/*
*--------------------------------------------------------------
* This module converts a counter value N into a reset value
* for an 8-bit LFSR. The count is initialized by "reset" high
* or "start" transition high. When the count is valid, it is
* latched into "dp" and the signal "done" is raised to indicate
* a valid new value of "dp".
*--------------------------------------------------------------
*/
module map9v3(clock, reset, start, N, dp, done, counter, sr);
input clock;
input start; // run at rising edge of start
input reset; // high is reset case ( run after reset)
input [8:0] N; // the number to divide by
output [8:0] dp; // these outputs drive an LFSR counter
output done;
output [7:0] counter;
output [7:0] sr;
reg [8:0] dp;
reg [7:0] sr;
reg [7:0] counter;
reg [1:0] startbuf;
reg done;
reg [2:0] state;
parameter INIT = 3'b000;
parameter RUN = 3'b001;
parameter ALMOSTDONE = 3'b010;
parameter DONE = 3'b011;
parameter WAIT = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset == 1) begin
dp <= 9'b0;
sr <= 8'b0;
counter <= 8'b0;
startbuf <= 2'b00;
done <= 0;
state <= INIT;
end else begin
if (state == INIT) begin
counter <= 255 - N[8:1] + 3;
sr <= 8'b0;
done <= 0;
state <= RUN;
end else if (state == RUN) begin
sr[7] <= sr[6];
sr[6] <= sr[5];
sr[5] <= sr[4];
sr[4] <= sr[3];
sr[3] <= sr[2];
sr[2] <= sr[1];
sr[1] <= sr[0];
sr[0] <= ~(sr[7] ^ sr[5] ^ sr[4] ^ sr[3]);
counter <= counter - 1;
if (counter == 0) begin
state <= ALMOSTDONE;
end
end else if (state == ALMOSTDONE) begin
dp[0] <= N[0];
dp[8:1] <= sr[7:0];
state <= DONE;
end else if (state == DONE) begin
done <= 1;
state <= WAIT;
end else if (state == WAIT) begin
if (startbuf == 2'b01) begin
state <= INIT;
end
end
startbuf <= {startbuf[0], start};
end
end
endmodule
