Still another ping. This is already ok sthen@ to import (but not yet in the tree).
Any other developer available to give it a try? Tarball re-attached. On 26/06/2020 18:19, Stuart Henderson wrote:
This is OK sthen@ to import. On 2020/06/26 16:35, Alessandro De Laurenzis wrote:Weekly ping. Tarball re-attached for your convenience. While there, I changed the master site from Github to opencircuitdesign.com (so we can avoid the on-the-fly generated archive). If you would like to play a bit with the port: - make a new directory (e.g. ./qflow-trial) and copy there the enclosed map9v3.v file; - change to that dir and run 'qflow gui'; - in the 'synthesys preparation' tab: * select map9v3.v as Verilog source file; * the 'Verilog module' field will be updated automatically; * click on 'Set stop' after every synthesis step; - click on 'Run' in the 'Preparation' row; - then run the other steps in sequence; - starting after the 'Placement', you'll be able to see the layout clicking on 'Edit Layout' (type 'v' in Magic window to see the full view).
-- Alessandro De Laurenzis [mailto:jus...@atlantide.mooo.com] Web: http://www.atlantide.mooo.com LinkedIn: http://it.linkedin.com/in/delaurenzis
qflow-1.4.83.tar.gz
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