Cyril, I have spent some time over the past few days reading up and thinking about page table schemes. Keep in mind that I am working in the dark with no source to refer to other than the AMD Opteron NUMA-smart sources.
As a reference we have this from Guy Shaw : http://polaris.blastwave.org/wiki/PolarisVirtualmemdetails http://polaris.blastwave.org/wiki/PolarisVirtualmem and a textbook picture : http://polaris.blastwave.org/attachment/wiki/PolarisVirtualmem/sol_vm.JPG >From a long long time ago I have this : http://www.blastwave.org/articles/BLS-0057/index.html I resureccted it and cleaned it up. I don't know what the current VA space architecture is and I can only assume we have a multi-level page table scheme. My hope is that we can architect a page table scheme with levels of indirection that grant a full address space to processes. A possible downside being fragmentation in PTE groups. These are axioms however. I have spent some time over the past months sketching thoughts and reading up things from the "OpenSolaris Community: Performance" pages. Hopefully we will be able to look at the memory management architecture implemented by Tom and Guy Shaw and then go forwards into either 32-bit or 64-bit address spaces. Dennis
