Ian, I have no doubt the synchronizer would work well for me ...in an ideal world. Even the Protel schematics I receive are often flawed with incorrect information, patterns, etc. I have no control over that, even when I provide input. For all of you taking the IPC CID courses, don't answer that question like I did..... The question was related to providing input back to the electrical engineer.....I answered " are you kidding?" During the course of a design, I might receive an update, hourly, each update still flawed. I learned to deal with it using the fastest method I could, just to keep pace with the errors and remain flexible. Perhaps, 5 percent of all the engineers I work with know how to create a proper schematic, a BOM, and run DRCs. Even less know what is required for PCB design. Seriously, some don't even understand a DRC matrix, or what the error means. This is 2003, hard to believe some of these guys are designing some of America's best fighting hardware.
Copper Pours another subject Well, I was working with Data Circuit's engineering department in California yesterday and resolved a copper pour issue. If you use the "NO HATCH" option, you can send gerbers with just copper outlines, annotate it with a FAB NOTE, then allow your fabricator to fill in copper areas. On large designs, this can be of great benefit for pouring copper on external layers. Copper pours can take hours on a large design, worst yet if it isn't right it has to pour again This is my tip of the Day Mike Reagan EDSI As far as copper pours....I just received an ----- Original Message ----- From: Ian Wilson <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Saturday, February 15, 2003 12:40 AM Subject: Re: [PEDA] A Question About Netlist Compare and Partially Matched Nets. Protel 99SE SP6. > On 09:18 AM 14/02/2003 -0500, Mike Reagan said: > >Ian, > >Time works against me. Some boards of which I have Protel schematics, I > >have found the synchronizer to take hours. > > I assume you are not using the "Assign Net to Connected Copper" option > within the synchronizer - I have found this to slow things down heaps. I > have not noticed a dramatic slow down of the synch with design size but > probably the biggest design I have done is quite modest by your standards. > > Mike, I am not surprised you have good reason for doing what you were > doing. I was mainly pointing out to others (and for the web searcher) that > the synch doesn't have this particular issue. I was quite sure you had > good reason not to use it in this case (though the cost and time spent > turning the PCB again would be more than the cost in your time doing using > the synch - in this case, I'd guess. So all you have to do is figure out > when you are about to make a mistake and spend the time doing the synch > instead of netlist load ... simple, eh! > > Ian > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
