MichaelB, While there may be some way somewhere to make Protel ignore those dogbones and vias, DRC wise, I don't think that there is a way to do it easily short of putting them on the schematic, possibly as test points, so that each of them actually becomes a real "net" it the netlist. You could turn off some of your Design Rules, but that would really just be asking for more trouble.
Myself, I have had the very same problem with the identical requirements (needing to take each BGA contact to the back of the board with a via), and I just live with the errors. I have accepted the fact that even if I were to do a perfect board in Protel 99 SE, that there would still be some little DRC error somewhere. Protel DRC just doesn't map to reality in all cases, as there is always some need for some special requirement that Protel just can't handle, so you look at the DRC error, and accept it as is, and live with the error in the report file and that little iridescent glow here and there on the on the screen. I find that the trick for me is to "reset" the errors once I have examined them, and that way they are not just sitting there staring me in the face as I continue working on the design. Respecting the layer stack up, I myself would prefer to go with 2 outer routing layers, 2 planes under that on each side, and then another 2 routing layers in the middle. But before you even get that far, I think that you need to ask whether any of the signals may have any special requirements, such as controlled impedance, or matched lengths, or isolation, or the necessity to be routed over a specific plane. I would also suggest that you definitely look into using separate complete layers for power and ground under your BGA as opposed to trying to juggle split planes. It may well be that due to the type of signals you are dealing with (LVDS / high speed / controlled impedance / susceptible to crosstalk), you might have to go with isolating the internal signal routing layers as layers 3 and 6 with the two power layers as 4 and 5. What type and size of BGA are you dealing with? Any special routing requirements? JaMi * * * * * * * * * ----- Original Message ----- From: "Michael Biggs" <[EMAIL PROTECTED]> To: "'Protel EDA Forum'" <[EMAIL PROTECTED]> Sent: Monday, June 02, 2003 1:20 PM Subject: [PEDA] eight-layer stackup > Anyone have a preferred method of stackup guidelines of web references to > layer stackups for 8 layers using four power planes and four signal layers? > I am torn between two methods being that I have two internal power planes. > Thanks for any help! > Also I have a couple of BGA's on this layout and when I run (using > Protel99SE) my DRC everything is great other than the "dogbones" I had to > route to the via on all the unused pins of the BGA. Any way to create rules > for this so I do not get violations during DRC? > Thanks again! > > MichaelB > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
