I have been following this discussion on DXP/2004 with some interest. I do many more FPGA designs than PCB designs and find it somewhat amusing that Altium are again trying to hit upon the FPGA market. Protel has previously tried to enter the FPGA (specifically Xilinx) with a schematic capture entry system. Although, I did play with it for some small time, I soon returned to the tried and proven tools that I used at the time. (What was worse, the Protel designs at the time had to be processed through part of the Orcad tool chain, and unless you had a particular Orcad tool for this function, you could not proceed to completion anyway!)
On the surface, it seems to be a logical extension of the engineering required in this day and age. However, the FPGA market in its own right seems to alter dramatically every few years. It was not that long ago that schematic capture was sufficient for most FPGA designs. Now VHDL/Verilog seem to be the default FPGA design entry tools, along with such tools as Mathcad, etc, to input (mathematical models) from a higher level viewpoint. (Mathcad like design entry generally spits out VHDL/Verilog based on the entered mathematical model, and can rapidly consume vast amounts of FPGA gates. Would anyone on this forum suggest that Altium have the necessary drive to compete in all these markets?) (Especially based on their previous track record?) As someone has stated, Xilinx do indeed give away a VERY GOOD design suite that gets you easily to several hundred k gates, and covers the entire design very nicely. (even schematic capture, if you wish) This tool even lets you easily alter specific synthesis topologies for individual modules at the click of a few buttons. (See the Xilinx Webpack) If you really wish vendor independence with FPGA's, you spend your dollars and go with one of the industry leaders, you do not use an unknown tool to get potentially wishy washy results. (Would you use Altium FPGA tools for a big design? I wouldn't!) For instance, Exemplar, which have been in the FPGA market for some time, producing such tools as Leonardo, Modelsim ... Their "foundry" tools have always been able to target multiple FPGA vendors, and Modelsim (as such) is the design verification tool. Expect to spend big bucks for the ability to target multiple vendors FPGA's, but the results can be well worth it!) Other companies also provide similar excellent FPGA retargeting ability within their tools as well. (Again, at a price ...)) I should point out that the tools from these vendors are aware of the internal architecture of the particular FPGA being targeted, and produce (semi optimal) results that differ based on the chosen device. I doubt that the Altium tools are going to be that specific! FPGA's look like a black box to most designers, but they do differ dramatically from one Vendor to the next. Even device families from one vendor can be significantly different in their internal features.) Unfortunately, design verification for FPGA's can easily take much longer than actually doing the design, the simulation "program" written in VHDL or Verilog can easily take 5..10 times the time to write. Final design verification also relies on back annotation of the actual targeted design to the simulation tools, and this always relies on the targeting tools from specific vendors. (Be they Xilinx, Altera, Actel, Atmel, Quicklogic, etc) Unless you also have the Foundry tools from each vendor you wish to attempt retargeting on, you really do NOT know if you are going to be successful. Since the pin outs for any FPGA is not standardised, FPGA retargeting must be achieved BEFORE PCB layout anyway. It would normally be done based on quoted price for the amount of k gates each vendor claims is equivalent to (some competitors) device. (Alas, comparisons between vendors of different FPGA devices is nowhere near that straight forward.) Complete PCB board simulation is also going to be problematical. While the concept of total simulation from schematics and FPGA logic through to the final PCB design sounds good, in actual implementation, it will be difficult beyond belief. It takes long enough just to set up a simple spice simulation. Now multiply this by many thousands, and consider how many PCB's you might be able to fully verify before fabrication proceeds. As it stands, the designer is generally aware of specific constraints for certain nets, and will attempt to ensure that these net constraints are met. (Or at least, he should indicate potential problems to the person doing the PCB design.) This does not even factor in many of the other potential issues with board design, like how topologies affect line impeadance, what the actual pin delay times (and capacitance, frequency response, etc). (Yes, I know that some vendors do have the relevant models for their device pins. Be aware that these are already somewhat simplified. Using these models though several serial connections is undoubtably going to introduce significant errors anyway.) Having said all this, I have not even looked at DXP, or 2004. I still use 99SE. (I have used virtually every Protel package over the years. Except their very first versions, which I saw, but never used as it was not as good as the package I used then.) In fact, from what I have seen on this forum about the change in methodologies from 99Se to later packages, I will stick to 99SE until I no longer have the option. (As someone stated, It will eventuate that 99SE will eventually break with some later operating system!) I still think the swap to an integrated database in 98/99/99se was a mistake that slows design loading beyond belief! (The last service pack for 99SE makes this even worse, playing a database compaction game every time you exit a project. (even if nothing has changed!) I must wonder though, where the Nanoboard fits in? what real use will this be to 99% of the users already out their? Certainly, I suspect very few will leverage any of the provided design. (Especially anyone who is already savvy in modern FPGA design!) Beyond the initial plug in and play with evaluation boards of this nature, very rarely are evaluation boards ever looked at again. (A few years later, they invariably end up in the trash!) As others have pointed out. Please work on the bread and butter parts of the package. (Schematic Capture, PCB layout, and to a lesser extent, simulation) Device footprint libraries could also be MUCH improved. (Ever tried to find an appropriate footprint within the Libraries from Protel? It's easier, faster, and more accurate to re-design your own!) There are so many area's within Protel packages that need cleanup (completion?) that I wonder why Altium have embarked down the track of being another "me too" FPGA tool at the risk of disenfranchising their current customers. It used to be obvious that the Protel team writing the Schematic capture did not communicate with the design team writing the PCB side. I imagine that this will only get worse in the future, as more engineering modules get ladled into the package. (What next? RF design tools? Full 3D design entry AKA ACAD?) There is so much more that can be said about this subject that I shudder! In fact, virtually a whole book could easily be written about individual topic area's within the Altium package. Having said all the above, Protel isn't all that bad. Its just that it could have been so much better, especially if some of the niggling deficiencies that have existed between one version to the next (and to the next ...) had been addressed, rather than going off in questionable directions, and releasing half baked tools that (occasionally?) destroy productivity. (Or having features in one tool that appear should propagate through to another tool, but in fact do not!) Cheers Harry -----Original Message----- From: Brooks,Bill [mailto:[EMAIL PROTECTED] Sent: Tuesday, April 13, 2004 9:36 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Would it not be nice? Yes I do get the option of assigning pins based upon the layout... but its frustrating and a manual process without Pin/Gate swap features in the Protel Software. Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 -----Original Message----- From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] Sent: Monday, April 12, 2004 3:34 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Would it not be nice? > -----Original Message----- > From: Brooks,Bill [mailto:[EMAIL PROTECTED] > Sent: Monday, April 12, 2004 6:43 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Would it not be nice? > > The key thing here John, may be, that Altium will need to > have a separate group of people to service the needs of their > "Simulation/Nanoboard" types from the PCB/SCH types. They > certainly have more issues to respond to. Bill This is true, unfortunately the bias seems to be towards the FPGA tools, I can understand why I guess, a lot more to consider than in just Capture/Layout but it has resulted in an over complex capture and layout environment with some clunky features, due to a simplified GUI approach not being practical for FPGA design as the FPGA design cycle is effectively within a software (scripted & text entry) environment. I do design as well, although my main focus is layout, I also deal with some major IC vendors for which I do the development/test boards and pre-layout analysis so they can decide on chip pin-out, similar to one of the target tasks of the new 2004 suite. To do this all I would have liked would have been to be able to import/export a ASIC pin list in ASCII, along the same idea as Orcad has done for years. Pin / Gate swapping might seem a small thing, but I would have been happier to see this feature in 2004 than new FPGA tools. > A full suite of tools says to me.. 'one size fits all'... or > more accurately would be like saying, 'This is the Family > Pack entertainment system, oh, you only wanted a tennis > racket? Well just you can store the ping pong table and the > billiards, The baseball bat and gloves, and the bonus camping > accessories in your garage and use them later...sorry, we > can't break up the set, there are no discounts'... > > Most of the PCB designers today don't need the simulation > tools, or the FPGA tools. Although we may need them in the > future when the boards we have to do are too complex to > properly layout, the simulation tools might help us deal with > impedance issues, line lengths, crosstalk, EMI, etc. See my above comment, I already do that anyway and have had some success in having ASIC design groups, amongst others, change pinouts (sometimes also test benches / simulations to suit external layout criteria) so that the test boards are ready and waiting for the devices at tape-out. In some cases the boards have been adopted as reference design boards and SDKs. Memory interfaces are the prime example, 64 bit/66MHz PCI being another, being able to have the IC designer move RAS/CAS/OE... because of layout needs makes life a lot easier for the layout engineer! How many times have we said 'who decided the pin locations on this damned device, they surely have not tried to lay it out first!' Altium seem to want to do a similar here, give the designer of FPGA the power to do this, I can see their goal with FPGA, rather than ASIC, I am just not a believer (yet) as I think the disciplines are too far removed from each other to be truly effective and very rarely completely under one persons control. I am used to a team environment, some say spoiled, but I am happy to play and share with others, it works better that way, a mans gotta know his limitations. > Besides, Xilinx gives away a very nice development package to > folks that want to work with their FPGA products... we > already have one. But I don't use it... the EE/FPGA engineer > uses it. The PCB guy(me)just does boards and schematics. And > the EE/FPGA guy does not layout the boards. But you can still control / advise on pinout if given the chance. > snip < > The ability to convert other CAD systems databases to Protel > is also a very powerful tool and should have been supported > more completely as the product has evolved. So many more > customers 'jump' to a product when it offers to convert their > old legacy databases into their new purchased format. But a lot of the importers planned were never implemented, the main concentration is Orcad. I had conversations a long time ago with Protel on a Cadstar importer, it never appeared. > I believe Altium/Protel has lost its 'common sense'... or > maybe PCB designer sense at the very least. Which is a great pity, as from my understanding, I am sure Mr Lomax will correct me if I am wrong (as he seems pretty hot on Protel history) that Protel tools were first created out of ones mans frustrations with the PCB layout tools available at the time, being clunky, inefficient and hard to use, so Protel was born. Circle of life eh? :-) John > > Bill Brooks > PCB Design Engineer , C.I.D., C.I.I. > Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 > > -----Original Message----- > From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] > Sent: Sunday, April 11, 2004 4:33 PM > To: 'Protel EDA Forum' > Subject: [PEDA] Would it not be nice? > > > Proper pin / gate swapping, a VERY high wish on all users > wish list, still > has not made it, but would have been nice, but we have FPGA > tools, so much > better than pin / gate swapping. > > John > > > > -----Original Message----- > > From: Nick Martin [mailto:[EMAIL PROTECTED] > > Sent: Monday, April 12, 2004 12:00 AM > > To: DXP Technical Forum > > Subject: Re: [dxp] NanoBoard > > > > snipped < > > > > I would be interested to know why you feel the need to use > > ISE and what areas of it are most interesting / useful to you. > > > > Best Regards, > > > > Nick > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
