My preference is to use functional pin designations something like
 k1a2
a1  k2

or

 d
s g

or

 c
e b

SOT23 devices, connectors, and diodes are the most common errors I have made
in my 18 years of layout work. A package change because of power,
availability, or
an alternate manufacture can confound the documentation. I have been
notified of problems
even when none exist because of pin numbering variations between silicon
manufactures.
I also find the design engineers appreciate that a schematic symbol
selection does not preclude
them from getting the layout correct even if the package changes during the
design process.

We use Orcad Capture for schematic entry and spice modeling. Protel for
layout.

Dave Eloranta
[EMAIL PROTECTED]



-----Original Message-----
From: Mira [mailto:[EMAIL PROTECTED]
Sent: Wednesday, July 14, 2004 9:58 PM
To: Protel EDA Forum
Subject: Re: [PEDA] SOT-23 pinout


Hi Dom,

The basic numbering is

 3
1 2

However many other variants of the pinout exist out
there.

Rule 1: Always check the datasheet.

Mira

--- Dom Bragge <[EMAIL PROTECTED]> wrote:
> When you organise your footprints, what pinout do
> you use for SOT-23's?
>
> Do you organise the pins...
>  -like shown in the attachment?
>  -or with pins 2&3 reversed?
>
> The bigger question really is: Where do you derive
> your pin numbering
> guidance from?
>
> I find that some datasheets just show the pin names
> against the actual
> pins (& cutout the middleman of *numbers*) thus
> avoiding the issue
> altogether. This doesn't help those of us who want
> to be able to use a
> common footprint across multiple designs.
>
> One answer is "define your own company standard",
> but if I chose
> against an industry standard, that'd be a bit silly
> wouldn't it.
>
> =====
> Dom Bragge CID
> Snr PCB Designer
> Sydney, Australia
>  ( 99SE sp6 )
>
> Find local movie times and trailers on Yahoo!
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