Hi Phillip,
Could you just elaborate a little on
The automatic generation of the *entire* FPGA's schematic sheet,
drawing all the wires, assigning nets to the wires, creating
the off sheet ports, creating the pin constraints file, and the FPGA pin
assignments can be passed down to the PCB automagically. It's all really very nice.
I assume that the schematic sheet that is created is simply a block with all the I/Os brought out as named nets? i.e. it doesn't attempt to interpret your VHDL and produce a schematic representation of your code?
I'm not arguing, just trying to see where the big benefit is. Right now I use the Xilinx software, and most design entry is via their schematic editor (crappy as it is!)and as little as possible in plain VHDL. Constraint entry is done on the schematic. Granted that I have to manually create a library entry with pin names and numbers in Protel, and I have to edit that every time I change something in the design, I agree that it would be nice to have it done automatically, but... am I missing something more?
Thanks for your input.
Roger
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