On Sun, May 26, 2019, 1:12 PM Barry Scott <ba...@barrys-emacs.org> wrote:
> You said this: "Well, depends on how we define narrow ... you are writing > probablythis email on a HDL designed machine ... and the entire world is > powered by HDL designed silicons. that is not small for me at all." > > Which I take to mean that because there are billions of chips in the world > there are billions of python users. And the change you want is justified > by the billions of python users. > I think the analogy is more like saying there are billions of Verilog users. Chips designed using this software are probably more numerous than are human beings, and nearly all humans use one or more such chips. This seems like a poor line of reasoning though. There are really only maybe tens of thousands of people in the world who use Verilog, and that is a nice target. Pursuing the same indirect reasoning, we could also claim there are billions of users of PSS/E, something I had not heard of until a web search a few minutes ago. Apparently this is software used in design of electrical distribution systems, required to make all of those ICs operate at all. Or software used for building the construction equipment needed to construct the power lines and factories where chips are made. Or... In any case, as I said, modifying the whole Python language to allow use of exactly the same symbols as Verilog users, seems foolish to me. That said, '<=' is already perfectly well available for non-blocking assignment. '=' cannot be overriden, but it occurs to me that a custom class could perfectly well use '==' for blocking assignment just by customizing a class. Yes, that would require 'foo.eq(bar)' for the old meaning of equality (or something similar), but it seems like assignment is more common than equality checks in Verilog.
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