Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 35e71ec53581fc8a90dfff1565e4ba344945cf80
https://github.com/qemu/qemu/commit/35e71ec53581fc8a90dfff1565e4ba344945cf80
Author: Shiva sagar Myana <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to
become wrongly sorted when executing g_slist_sort. Fix this by always
returning -1 or 1 from g_cmp_ids based on the ID comparison instead.
Also, if two message IDs are the same, sort them by using their index and
transmit the message at the lowest index first.
Signed-off-by: Shiva sagar Myana <[email protected]>
Reviewed-by: Francisco Iglesias <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7edca16e745ca2105066832c9da34077af41347e
https://github.com/qemu/qemu/commit/7edca16e745ca2105066832c9da34077af41347e
Author: Marcin Juszkiewicz <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: switch to 1GHz timer frequency
Updated firmware for QEMU CI is already in merge queue so we can move
platform to be future proof.
All supported cpus work fine with 1GHz timer frequency when firmware is
fresh enough.
Signed-off-by: Marcin Juszkiewicz <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7175a562f157d39725ab396e39c1e8e410d206b3
https://github.com/qemu/qemu/commit/7175a562f157d39725ab396e39c1e8e410d206b3
Author: Edgar E. Iglesias <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/intc/gic_internal.h
Log Message:
-----------
hw/intc/arm_gic: Fix deactivation of SPI lines
Julien reported that he has seen strange behaviour when running
Xen on QEMU using GICv2. When Xen migrates a guest's vCPU from
one pCPU to another while the vCPU is handling an interrupt, the
guest is unable to properly deactivate interrupts.
Looking at it a little closer, our GICv2 model treats
deactivation of SPI lines as if they were PPI's, i.e banked per
CPU core. The state for active interrupts should only be banked
for PPI lines, not for SPI lines.
Make deactivation of SPI lines unbanked, similar to how we
handle writes to GICD_ICACTIVER.
Reported-by: Julien Grall <[email protected]>
Signed-off-by: Edgar E. Iglesias <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9b113a09ff34857d463c130faa873c7b6fc4a004
https://github.com/qemu/qemu/commit/9b113a09ff34857d463c130faa873c7b6fc4a004
Author: Sebastian Huber <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
Fix the system bus interrupt line to CPU core assignment.
Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores")
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 057f7680f4ed1cc27a0520c0628bfb94f850c56a
https://github.com/qemu/qemu/commit/057f7680f4ed1cc27a0520c0628bfb94f850c56a
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI
Since commit 83aa1baa069c we have been running the build for Coverity
Scan as a Gitlab CI job, rather than the old setup where it was run
on a local developer's machine. This is working well, but the
absolute paths of files are different for the Gitlab CI job, which
means that the regexes we use to identify Coverity components no
longer work. With Gitlab CI builds the file paths are of the form
/builds/qemu-project/qemu/accel/kvm/kvm-all.c
rather than the old
/qemu/accel/kvm/kvm-all.c
and our regexes all don't match.
Update all the regexes to start with .*/qemu/ . This will hopefully
avoid the need to change them again in future if the build path
changes again.
This change was made with a search-and-replace of (/qemu)?
to .*/qemu .
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 7966cf71d36560024f07863fef26e265b2941f25
https://github.com/qemu/qemu/commit/7966cf71d36560024f07863fef26e265b2941f25
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
scripts/coverity-scan/COMPONENTS.md: Fix 'char' component
The 'char' component:
* includes the no-longer-present qemu-char.c, which has been
long since split into the chardev/ backend code
* also includes the hw/char devices
Split it into two components:
* char is the hw/char devices
* chardev is the chardev backends
with regexes matching our current sources.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 9c43c934d1a998d46a4a15675950f0c5eccb6b4c
https://github.com/qemu/qemu/commit/9c43c934d1a998d46a4a15675950f0c5eccb6b4c
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to
the crypto component
host/include/*/host/crypto/ are relatively new headers; add them
to the crypto component.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 8e055eab4fea581644cd6df28984f1a2a5fde08e
https://github.com/qemu/qemu/commit/8e055eab4fea581644cd6df28984f1a2a5fde08e
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
scripts/coverity-scan/COMPONENTS.md: Fix monitor component
Update the 'monitor' component:
* qapi/ and monitor/ are now subdirectories
* add job-qmp.c
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 5d173f30f6828a1a4e6133eb324cc4ab0277a06d
https://github.com/qemu/qemu/commit/5d173f30f6828a1a4e6133eb324cc4ab0277a06d
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs
Add libqmp to the testlibs component.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: ff8aff01fa20c4fd5bbe46e1d25fbefdf996ef73
https://github.com/qemu/qemu/commit/ff8aff01fa20c4fd5bbe46e1d25fbefdf996ef73
Author: Zheyu Ma <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/timer/a9gtimer.c
Log Message:
-----------
hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
This commit updates the a9_gtimer_get_current_cpu() function to handle
cases where QTest is enabled. When QTest is used, it returns 0 instead
of dereferencing the current_cpu, which can be NULL. This prevents the
program from crashing during QTest runs.
Reproducer:
cat << EOF | qemu-system-aarch64 -display \
none -machine accel=qtest, -m 512M -machine npcm750-evb -qtest stdio
writel 0xf03fe20c 0x26d7468c
EOF
Signed-off-by: Zheyu Ma <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 813b59e8b8ab5d284672e0bbd79173df2e25e01d
https://github.com/qemu/qemu/commit/813b59e8b8ab5d284672e0bbd79173df2e25e01d
Author: Zheyu Ma <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/usb/hcd-dwc2.c
Log Message:
-----------
hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
This commit modifies the dwc2_hsotg_read() and dwc2_hsotg_write() functions
to handle invalid address access gracefully. Instead of using
g_assert_not_reached(), which causes the program to abort, the functions
now log an error message and return a default value for reads or do
nothing for writes.
This change prevents the program from aborting and provides clear log
messages indicating when an invalid memory address is accessed.
Reproducer:
cat << EOF | qemu-system-aarch64 -display none \
-machine accel=qtest, -m 512M -machine raspi2b -m 1G -nodefaults \
-usb -drive file=null-co://,if=none,format=raw,id=disk0 -device \
usb-storage,port=1,drive=disk0 -qtest stdio
readl 0x3f980dfb
EOF
Signed-off-by: Zheyu Ma <[email protected]>
Reviewed-by: Paul Zimmerman <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9ed2fb65cc827904241dee189c801c10079c2fe3
https://github.com/qemu/qemu/commit/9ed2fb65cc827904241dee189c801c10079c2fe3
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Add serial aliases in DTB
If there is more than one UART in the DTB, then there is no guarantee
on which order a guest is supposed to initialise them. The standard
solution to this is "serialN" entries in the "/aliases" node of the
dtb which give the nodename of the UARTs.
At the moment we only have two UARTs in the DTB when one is for
the Secure world and one for the Non-Secure world, so this isn't
really a problem. However if we want to add a second NS UART we'll
need the aliases to ensure guests pick the right one.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: fe22cba940d82e93818135c044afed4099056628
https://github.com/qemu/qemu/commit/fe22cba940d82e93818135c044afed4099056628
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]
We're going to make the second UART not always a secure-only device.
Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0
and VIRT_UART1 accordingly.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: e7100972f2df313d1e47a0714aed968991437e86
https://github.com/qemu/qemu/commit/e7100972f2df313d1e47a0714aed968991437e86
Author: Peter Maydell <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: allow creation of a second NonSecure UART
For some use-cases, it is helpful to have more than one UART
available to the guest. If the second UART slot is not already used
for a TrustZone Secure-World-only UART, create it as a NonSecure UART
only when the user provides a serial backend (e.g. via a second
-serial command line option).
This avoids problems where existing guest software only expects a
single UART, and gets confused by the second UART in the DTB. The
major example of this is older EDK2 firmware, which will send the
GRUB bootloader output to UART1 and the guest serial output to UART0.
Users who want to use both UARTs with a guest setup including EDK2
are advised to update to EDK2 release edk2-stable202311 or newer.
(The prebuilt EDK2 blobs QEMU upstream provides are new enough.)
The relevant EDK2 changes are the ones described here:
https://bugzilla.tianocore.org/show_bug.cgi?id=4577
Inspired-by: Axel Heider <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Tested-by: Laszlo Ersek <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: dda533087ad5559674ff486e7031c88dc01e0abd
https://github.com/qemu/qemu/commit/dda533087ad5559674ff486e7031c88dc01e0abd
Author: Zhenyu Zhang <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu
CPUs
Multiple warning messages and corresponding backtraces are observed when Linux
guest is booted on the host with Fujitsu CPUs. One of them is shown as below.
[ 0.032443] ------------[ cut here ]------------
[ 0.032446] uart-pl011 9000000.pl011: ARCH_DMA_MINALIGN smaller than
CTR_EL0.CWG (128 < 256)
[ 0.032454] WARNING: CPU: 0 PID: 1 at arch/arm64/mm/dma-mapping.c:54
arch_setup_dma_ops+0xbc/0xcc
[ 0.032470] Modules linked in:
[ 0.032475] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-452.el9.aarch64
[ 0.032481] Hardware name: linux,dummy-virt (DT)
[ 0.032484] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 0.032490] pc : arch_setup_dma_ops+0xbc/0xcc
[ 0.032496] lr : arch_setup_dma_ops+0xbc/0xcc
[ 0.032501] sp : ffff80008003b860
[ 0.032503] x29: ffff80008003b860 x28: 0000000000000000 x27: ffffaae4b949049c
[ 0.032510] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000000
[ 0.032517] x23: 0000000000000100 x22: 0000000000000000 x21: 0000000000000000
[ 0.032523] x20: 0000000100000000 x19: ffff2f06c02ea400 x18: ffffffffffffffff
[ 0.032529] x17: 00000000208a5f76 x16: 000000006589dbcb x15: ffffaae4ba071c89
[ 0.032535] x14: 0000000000000000 x13: ffffaae4ba071c84 x12: 455f525443206e61
[ 0.032541] x11: 68742072656c6c61 x10: 0000000000000029 x9 : ffffaae4b7d21da4
[ 0.032547] x8 : 0000000000000029 x7 : 4c414e494d5f414d x6 : 0000000000000029
[ 0.032553] x5 : 000000000000000f x4 : ffffaae4b9617a00 x3 : 0000000000000001
[ 0.032558] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff2f06c029be40
[ 0.032564] Call trace:
[ 0.032566] arch_setup_dma_ops+0xbc/0xcc
[ 0.032572] of_dma_configure_id+0x138/0x300
[ 0.032591] amba_dma_configure+0x34/0xc0
[ 0.032600] really_probe+0x78/0x3dc
[ 0.032614] __driver_probe_device+0x108/0x160
[ 0.032619] driver_probe_device+0x44/0x114
[ 0.032624] __device_attach_driver+0xb8/0x14c
[ 0.032629] bus_for_each_drv+0x88/0xe4
[ 0.032634] __device_attach+0xb0/0x1e0
[ 0.032638] device_initial_probe+0x18/0x20
[ 0.032643] bus_probe_device+0xa8/0xb0
[ 0.032648] device_add+0x4b4/0x6c0
[ 0.032652] amba_device_try_add.part.0+0x48/0x360
[ 0.032657] amba_device_add+0x104/0x144
[ 0.032662] of_amba_device_create.isra.0+0x100/0x1c4
[ 0.032666] of_platform_bus_create+0x294/0x35c
[ 0.032669] of_platform_populate+0x5c/0x150
[ 0.032672] of_platform_default_populate_init+0xd0/0xec
[ 0.032697] do_one_initcall+0x4c/0x2e0
[ 0.032701] do_initcalls+0x100/0x13c
[ 0.032707] kernel_init_freeable+0x1c8/0x21c
[ 0.032712] kernel_init+0x28/0x140
[ 0.032731] ret_from_fork+0x10/0x20
[ 0.032735] ---[ end trace 0000000000000000 ]---
In Linux, a check is applied to every device which is exposed through
device-tree node. The warning message is raised when the device isn't
DMA coherent and the cache line size is larger than ARCH_DMA_MINALIGN
(128 bytes). The cache line is sorted from CTR_EL0[CWG], which corresponds
to 256 bytes on the guest CPUs. The DMA coherent capability is claimed
through 'dma-coherent' in their device-tree nodes or parent nodes.
This happens even when the device doesn't implement or use DMA at all,
for legacy reasons.
Fix the issue by adding 'dma-coherent' property to the device-tree root
node, meaning all devices are capable of DMA coherent by default.
This both suppresses the spurious kernel warnings and also guards
against possible future QEMU bugs where we add a DMA-capable device
and forget to mark it as dma-coherent.
Signed-off-by: Zhenyu Zhang <[email protected]>
Reviewed-by: Gavin Shan <[email protected]>
Reviewed-by: Donald Dutile <[email protected]
Reviewed-by: Jonathan Cameron <[email protected]>
Message-id: [email protected]
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d338b5a80922433a2c4a63986b41f82ae4137dfc
https://github.com/qemu/qemu/commit/d338b5a80922433a2c4a63986b41f82ae4137dfc
Author: Zheyu Ma <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/misc/exynos4210_rng.c
Log Message:
-----------
hw/misc: Set valid access size for Exynos4210 RNG
The Exynos4210 RNG module requires 32-bit (4-byte) accesses to its registers.
According to the User Manual Section 25.3[1], the registers for RNG operations
are 32-bit. This change ensures that the memory region operations for the
RNG module enforce the correct access sizes, preventing invalid memory accesses.
[1]
http://www.mediafire.com/view/8ly2fqls3c9c31c/Exynos_4412_SCP_Users_Manual_Ver.0.10.00_Preliminary0.pdf
Reproducer:
cat << EOF | qemu-system-aarch64 -display none \
-machine accel=qtest, -m 512M -machine smdkc210 -qtest stdio
readb 0x10830454
EOF
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Zheyu Ma <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 53aaa88105e2f9cbef3a4d17df007dbdf985d6e2
https://github.com/qemu/qemu/commit/53aaa88105e2f9cbef3a4d17df007dbdf985d6e2
Author: David Hubbard <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M hw/usb/hcd-ohci.c
M hw/usb/trace-events
Log Message:
-----------
hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1
This changes the way the ohci emulation handles a Transfer Descriptor
with "Buffer End" set to "Current Buffer Pointer" - 1, specifically
in the case of a zero-length packet.
The OHCI spec 4.3.1.2 Table 4-2 specifies td.cbp to be zero for a
zero-length packet. Peter Maydell tracked down commit 1328fe0c32
(hw: usb: hcd-ohci: check len and frame_number variables) where qemu
started checking this according to the spec.
What this patch does is loosen the qemu ohci implementation to allow a
zero-length packet if td.be (Buffer End) is set to td.cbp - 1, and with a
non-zero td.cbp value.
The spec is unclear whether this is valid or not -- it is not the
clearly documented way to send a zero length TD (which is CBP=BE=0),
but it isn't specifically forbidden. Actual hw seems to be ok with it.
Does any OS rely on this behavior? There have been no reports to
qemu-devel of this problem.
This is attempting to have qemu behave like actual hardware,
but this is just a minor change.
With a tiny OS[1] that boots and executes a test, the issue can be seen:
* OS that sends USB requests to a USB mass storage device
but sends td.cbp = td.be + 1
* qemu 4.2
* qemu HEAD (4e66a0854)
* Actual OHCI controller (hardware)
Command line:
qemu-system-x86_64 -m 20 \
-device pci-ohci,id=ohci \
-drive if=none,format=raw,id=d,file=testmbr.raw \
-device usb-storage,bus=ohci.0,drive=d \
--trace "usb_*" --trace "ohci_*" -D qemu.log
Results are:
qemu 4.2 | qemu HEAD | actual HW
-----------+------------+-----------
works fine | ohci_die() | works fine
Tip: if the flags "-serial pty -serial stdio" are added to the command line
the test will output USB requests like this:
Testing qemu HEAD:
> Free mem 2M ohci port2 conn FS
> setup { 80 6 0 1 0 0 8 0 }
> ED info=80000 { mps=8 en=0 d=0 } tail=c20920
> td0 c20880 nxt=c20960 f2000000 setup cbp=c20900 be=c20907
> td1 c20960 nxt=c20980 f3140000 in cbp=c20908 be=c2090f
> td2 c20980 nxt=c20920 f3080000 out cbp=c20910 be=c2090f ohci20 host err
> usb stopped
And in qemu.log:
usb_ohci_iso_td_bad_cc_overrun ISO_TD start_offset=0x00c20910 >
next_offset=0x00c2090f
Testing qemu 4.2:
> Free mem 2M ohci port2 conn FS
> setup { 80 6 0 1 0 0 8 0 }
> ED info=80000 { mps=8 en=0 d=0 } tail=620920
> td0 620880 nxt=620960 f2000000 setup cbp=620900 be=620907 cbp=0
> be=620907
> td1 620960 nxt=620980 f3140000 in cbp=620908 be=62090f cbp=0
> be=62090f
> td2 620980 nxt=620920 f3080000 out cbp=620910 be=62090f cbp=0
> be=62090f
> rx { 12 1 0 2 0 0 0 8 }
> setup { 0 5 1 0 0 0 0 0 } tx {}
> ED info=80000 { mps=8 en=0 d=0 } tail=620880
> td0 620920 nxt=620960 f2000000 setup cbp=620900 be=620907 cbp=0
> be=620907
> td1 620960 nxt=620880 f3100000 in cbp=620908 be=620907 cbp=0
> be=620907
> setup { 80 6 0 1 0 0 12 0 }
> ED info=80001 { mps=8 en=0 d=1 } tail=620960
> td0 620880 nxt=6209c0 f2000000 setup cbp=620920 be=620927 cbp=0
> be=620927
> td1 6209c0 nxt=6209e0 f3140000 in cbp=620928 be=620939 cbp=0
> be=620939
> td2 6209e0 nxt=620960 f3080000 out cbp=62093a be=620939 cbp=0
> be=620939
> rx { 12 1 0 2 0 0 0 8 f4 46 1 0 0 0 1 2 3 1 }
> setup { 80 6 0 2 0 0 0 1 }
> ED info=80001 { mps=8 en=0 d=1 } tail=620880
> td0 620960 nxt=6209a0 f2000000 setup cbp=620a20 be=620a27 cbp=0
> be=620a27
> td1 6209a0 nxt=6209c0 f3140004 in cbp=620a28 be=620b27 cbp=620a48
> be=620b27
> td2 6209c0 nxt=620880 f3080000 out cbp=620b28 be=620b27 cbp=0
> be=620b27
> rx { 9 2 20 0 1 1 4 c0 0 9 4 0 0 2 8 6 50 0 7 5 81 2 40 0 0 7 5 2 2 40 0 0
> }
> setup { 0 9 1 0 0 0 0 0 } tx {}
> ED info=80001 { mps=8 en=0 d=1 } tail=620900
> td0 620880 nxt=620940 f2000000 setup cbp=620a00 be=620a07 cbp=0
> be=620a07
> td1 620940 nxt=620900 f3100000 in cbp=620a08 be=620a07 cbp=0
> be=620a07
[1] The OS disk image has been emailed to [email protected], [email protected],
and [email protected]:
* testCbpOffBy1.img.xz
* sha256: f87baddcb86de845de12f002c698670a426affb40946025cc32694f9daa3abed
Signed-off-by: David Hubbard <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a
https://github.com/qemu/qemu/commit/3b36cead6ecc0e40edb8b2f3e253baa01ebc1e9a
Author: Xiong Yining <[email protected]>
Date: 2024-06-21 (Fri, 21 Jun 2024)
Changed paths:
M docs/system/arm/sbsa.rst
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
Enable CPU cluster support on SbsaQemu platform, so that users can
specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And
this topology can be passed to the firmware through /cpus/topology
Device Tree.
Signed-off-by: Xiong Yining <[email protected]>
Reviewed-by: Marcin Juszkiewicz <[email protected]>
Reviewed-by: Leif Lindholm <[email protected]>
Message-id: [email protected]
Tested-by: Marcin Juszkiewicz <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: c9ba79baca7c673098361e3a687f72d458e0d18a
https://github.com/qemu/qemu/commit/c9ba79baca7c673098361e3a687f72d458e0d18a
Author: Richard Henderson <[email protected]>
Date: 2024-06-22 (Sat, 22 Jun 2024)
Changed paths:
M docs/system/arm/sbsa.rst
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/arm/xilinx_zynq.c
M hw/intc/gic_internal.h
M hw/misc/exynos4210_rng.c
M hw/net/can/xlnx-versal-canfd.c
M hw/timer/a9gtimer.c
M hw/usb/hcd-dwc2.c
M hw/usb/hcd-ohci.c
M hw/usb/trace-events
M include/hw/arm/virt.h
M scripts/coverity-scan/COMPONENTS.md
Log Message:
-----------
Merge tag 'pull-target-arm-20240622' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
* hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
* hw/intc/arm_gic: Fix deactivation of SPI lines
* hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
* hw/misc: Set valid access size for Exynos4210 RNG
* hw/arm/sbsa-ref: switch to 1GHz timer frequency
* hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
* hw/arm/virt: allow creation of a second NonSecure UART
* hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu
CPUs
* scripts/coverity-scan/COMPONENTS.md: update component regexes
* hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
* hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1
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# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 22 Jun 2024 05:06:00 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
* tag 'pull-target-arm-20240622' of
https://git.linaro.org/people/pmaydell/qemu-arm:
hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine
hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1
hw/misc: Set valid access size for Exynos4210 RNG
hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu
CPUs
hw/arm/virt: allow creation of a second NonSecure UART
hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]
hw/arm/virt: Add serial aliases in DTB
hw/usb/hcd-dwc2: Handle invalid address access in read and write functions
hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu
scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs
scripts/coverity-scan/COMPONENTS.md: Fix monitor component
scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to
the crypto component
scripts/coverity-scan/COMPONENTS.md: Fix 'char' component
scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI
hw/arm/xilinx_zynq: Fix IRQ/FIQ routing
hw/intc/arm_gic: Fix deactivation of SPI lines
hw/arm/sbsa-ref: switch to 1GHz timer frequency
hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/ffeddb979400...c9ba79baca7c
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