Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: bb89c20b993dd639bd0755e7538ab92beb7ccc2c
https://github.com/qemu/qemu/commit/bb89c20b993dd639bd0755e7538ab92beb7ccc2c
Author: Xiaoyao Li <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f]
Currently, QEMU always constructs a all-zero CPUID entry for
CPUID[0xD 0x3f].
It's meaningless to construct such a leaf as the end of leaf 0xD. Rework
the logic of how subleaves of 0xD are constructed to get rid of such
all-zero value of subleaf 0x3f.
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 078301407f861ef4ebe7b78d1a8221f1f158a3b0
https://github.com/qemu/qemu/commit/078301407f861ef4ebe7b78d1a8221f1f158a3b0
Author: Xiaoyao Li <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Enable fdp-excptn-only and zero-fcs-fds
- CPUID.(EAX=07H,ECX=0H):EBX[bit 6]: x87 FPU Data Pointer updated only
on x87 exceptions if 1.
- CPUID.(EAX=07H,ECX=0H):EBX[bit 13]: Deprecates FPU CS and FPU DS
values if 1. i.e., X87 FCS and FDS are always zero.
Define names for them so that they can be exposed to guest with -cpu host.
Also define the bit field MACROs so that named cpu models can add it as
well in the future.
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 8df284199ba57a4caa57e07a5691f6c529200ae0
https://github.com/qemu/qemu/commit/8df284199ba57a4caa57e07a5691f6c529200ae0
Author: Xiaoyao Li <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Construct CPUID 2 as stateful iff times > 1
When times == 1, the CPUID leaf 2 is not stateful.
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e0adbaf598581e8d26cb1c0dcac58f8c5d4314e5
https://github.com/qemu/qemu/commit/e0adbaf598581e8d26cb1c0dcac58f8c5d4314e5
Author: Xiaoyao Li <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Make invtsc migratable when user sets tsc-khz explicitly
When user sets tsc-frequency explicitly, the invtsc feature is actually
migratable because the tsc-frequency is supposed to be fixed during the
migration.
See commit d99569d9d856 ("kvm: Allow invtsc migration if tsc-khz
is set explicitly") for referrence.
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5e619643a3500e6cf91af9fec2143abf3a77f5e4
https://github.com/qemu/qemu/commit/5e619643a3500e6cf91af9fec2143abf3a77f5e4
Author: Chao Gao <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Add more features enumerated by CPUID.7.2.EDX
Following 5 bits in CPUID.7.2.EDX are supported by KVM. Add their
supports in QEMU. Each of them indicates certain bits of IA32_SPEC_CTRL
are supported. Those bits can control CPU speculation behavior which can
be used to defend against side-channel attacks.
bit0: intel-psfd
if 1, indicates bit 7 of the IA32_SPEC_CTRL MSR is supported. Bit 7 of
this MSR disables Fast Store Forwarding Predictor without disabling
Speculative Store Bypass
bit1: ipred-ctrl
If 1, indicates bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported.
Bit 3 of this MSR enables IPRED_DIS control for CPL3. Bit 4 of this
MSR enables IPRED_DIS control for CPL0/1/2
bit2: rrsba-ctrl
If 1, indicates bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported.
Bit 5 of this MSR disables RRSBA behavior for CPL3. Bit 6 of this MSR
disables RRSBA behavior for CPL0/1/2
bit3: ddpd-u
If 1, indicates bit 8 of the IA32_SPEC_CTRL MSR is supported. Bit 8 of
this MSR disables Data Dependent Prefetcher.
bit4: bhi-ctrl
if 1, indicates bit 10 of the IA32_SPEC_CTRL MSR is supported. Bit 10
of this MSR enables BHI_DIS_S behavior.
Signed-off-by: Chao Gao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 3d3e1d045c82b214b0e0da42654003fbfc560059
https://github.com/qemu/qemu/commit/3d3e1d045c82b214b0e0da42654003fbfc560059
Author: Gao Shiyuan <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/machine.c
Log Message:
-----------
target/i386: Add support save/load HWCR MSR
KVM commit 191c8137a939 ("x86/kvm: Implement HWCR support")
introduced support for emulating HWCR MSR.
Add support for QEMU to save/load this MSR for migration purposes.
Signed-off-by: Gao Shiyuan <[email protected]>
Signed-off-by: Wang Liang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 955645be897a45d27ec0d4a87839cb04ab06576f
https://github.com/qemu/qemu/commit/955645be897a45d27ec0d4a87839cb04ab06576f
Author: Vitaly Kuznetsov <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/cpu.c
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Fix conditional CONFIG_SYNDBG enablement
Putting HYPERV_FEAT_SYNDBG entry under "#ifdef CONFIG_SYNDBG" in
'kvm_hyperv_properties' array is wrong: as HYPERV_FEAT_SYNDBG is not
the highest feature number, the result is an empty (zeroed) entry in
the array (and not a skipped entry!). hyperv_feature_supported() is
designed to check that all CPUID bits are set but for a zeroed
feature in 'kvm_hyperv_properties' it returns 'true' so QEMU considers
HYPERV_FEAT_SYNDBG as always supported, regardless of whether KVM host
actually supports it.
To fix the issue, leave HYPERV_FEAT_SYNDBG's definition in
'kvm_hyperv_properties' array, there's nothing wrong in having it defined
even when 'CONFIG_SYNDBG' is not set. Instead, put "hv-syndbg" CPU property
under '#ifdef CONFIG_SYNDBG' to alter the existing behavior when the flag
is silently skipped in !CONFIG_SYNDBG builds.
Leave an 'assert' sentinel in hyperv_feature_supported() making sure there
are no 'holes' or improperly defined features in 'kvm_hyperv_properties'.
Fixes: d8701185f40c ("hw: hyperv: Initial commit for Synthetic Debugging
device")
Signed-off-by: Vitaly Kuznetsov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 293f1380d4b33a9b8ae2f4cb7e97e2aed6df6be4
https://github.com/qemu/qemu/commit/293f1380d4b33a9b8ae2f4cb7e97e2aed6df6be4
Author: Vitaly Kuznetsov <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/system/i386/hyperv.rst
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: Exclude 'hv-syndbg' from 'hv-passthrough'
Windows with Hyper-V role enabled doesn't boot with 'hv-passthrough' when
no debugger is configured, this significantly limits the usefulness of the
feature as there's no support for subtracting Hyper-V features from CPU
flags at this moment (e.g. "-cpu host,hv-passthrough,-hv-syndbg" does not
work). While this is also theoretically fixable, 'hv-syndbg' is likely
very special and unneeded in the default set. Genuine Hyper-V doesn't seem
to enable it either.
Introduce 'skip_passthrough' flag to 'kvm_hyperv_properties' and use it as
one-off to skip 'hv-syndbg' when enabling features in 'hv-passthrough'
mode. Note, "-cpu host,hv-passthrough,hv-syndbg" can still be used if
needed.
As both 'hv-passthrough' and 'hv-syndbg' are debug features, the change
should not have any effect on production environments.
Signed-off-by: Vitaly Kuznetsov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 25d098117c5da9a0f3a06c8c8b9a2d3ed0a58eb8
https://github.com/qemu/qemu/commit/25d098117c5da9a0f3a06c8c8b9a2d3ed0a58eb8
Author: Vitaly Kuznetsov <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/kvm/hyperv.c
Log Message:
-----------
target/i386: Make sure SynIC state is really updated before KVM_RUN
'hyperv_synic' test from KVM unittests was observed to be flaky on certain
hardware (hangs sometimes). Debugging shows that the problem happens in
hyperv_sint_route_new() when the test tries to set up a new SynIC
route. The function bails out on:
if (!synic->sctl_enabled) {
goto cleanup;
}
but the test writes to HV_X64_MSR_SCONTROL just before it starts
establishing SINT routes. Further investigation shows that
synic_update() (called from async_synic_update()) happens after the SINT
setup attempt and not before. Apparently, the comment before
async_safe_run_on_cpu() in kvm_hv_handle_exit() does not correctly describe
the guarantees async_safe_run_on_cpu() gives. In particular, async worked
added to a CPU is actually processed from qemu_wait_io_event() which is not
always called before KVM_RUN, i.e. kvm_cpu_exec() checks whether an exit
request is pending for a CPU and if not, keeps running the vCPU until it
meets an exit it can't handle internally. Hyper-V specific MSR writes are
not automatically trigger an exit.
Fix the issue by simply raising an exit request for the vCPU where SynIC
update was queued. This is not a performance critical path as SynIC state
does not get updated so often (and async_safe_run_on_cpu() is a big hammer
anyways).
Reported-by: Jan Richter <[email protected]>
Signed-off-by: Vitaly Kuznetsov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5ae5a52cbbda7382ef795be82505e9dbebddc1df
https://github.com/qemu/qemu/commit/5ae5a52cbbda7382ef795be82505e9dbebddc1df
Author: Vitaly Kuznetsov <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M docs/system/i386/hyperv.rst
Log Message:
-----------
docs/system: Add recommendations to Hyper-V enlightenments doc
While hyperv.rst already has all currently implemented Hyper-V
enlightenments documented, it may be unclear what is the recommended set to
achieve the best result. Add the corresponding section to the doc.
Signed-off-by: Vitaly Kuznetsov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 62e61b0f1b3e841533314c443f2af117d7c9071c
https://github.com/qemu/qemu/commit/62e61b0f1b3e841533314c443f2af117d7c9071c
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: convert bit test instructions to new decoder
Code generation was rewritten; it reuses the same trick to use the
CC_OP_SAR values for cc_op, but it tries to use CC_OP_ADCX or CC_OP_ADCOX
instead of CC_OP_EFLAGS. This is a tiny bit more efficient in the
common case where only CF is checked in the resulting flags.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 84f505f8ba50e183a808bc28b3075d94578e57b5
https://github.com/qemu/qemu/commit/84f505f8ba50e183a808bc28b3075d94578e57b5
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: decode address before going back to translate.c
There are now relatively few unconverted opcodes in translate.c (there
are 13 of them including 8 for x87), and all of them have the same
format with a mod/rm byte and no immediate. A good next step is
to remove the early bail out to disas_insn_x87/disas_insn_old,
instead giving these legacy translator functions the same prototype
as the other gen_* functions.
To do this, the X86DecodeInsn can be passed down to the places that
used to fetch address bytes from the instruction stream. To make
sure that everything is done cleanly, the CPUX86State* argument is
removed.
As part of the unification, the gen_lea_modrm() name is now free,
so rename gen_load_ea() to gen_lea_modrm(). This is as good a name
and it makes the changes to translate.c easier to review.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0df4e13e6cdceb3ab2eb5d2e4c7c744444a10ac6
https://github.com/qemu/qemu/commit/0df4e13e6cdceb3ab2eb5d2e4c7c744444a10ac6
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder
The gen_cmpxchg8b and gen_cmpxchg16b functions even have the correct
prototype already; the only thing that needs to be done is removing the
gen_lea_modrm() call.
This moves the last LOCK-enabled instructions to the new decoder. It is
now possible to assume that gen_multi0F is called only after checking
that PREFIX_LOCK was not specified.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d541f43ee73e00274fe58cb8db1f8a52bbd63ec0
https://github.com/qemu/qemu/commit/d541f43ee73e00274fe58cb8db1f8a52bbd63ec0
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: do not check PREFIX_LOCK in old-style decoder
It is already checked before getting there.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 6e92720981d8f4d36b18c6da18e4773a56c51245
https://github.com/qemu/qemu/commit/6e92720981d8f4d36b18c6da18e4773a56c51245
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
Log Message:
-----------
target/i386: list instructions still in translate.c
Group them so that it is easier to figure out which two-byte opcodes to
tackle together.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 906fdcf1ab480c1640519d25a6a9eb06d156f10e
https://github.com/qemu/qemu/commit/906fdcf1ab480c1640519d25a6a9eb06d156f10e
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: assert that cc_op* and pc_save are preserved
Now all decoding has been done before any code generation.
There is no need anymore to save and restore cc_op* and
pc_save but, for the time being, assert that this is indeed
the case.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 947679f86c24786317967ff9bbe1ef2ea1293dda
https://github.com/qemu/qemu/commit/947679f86c24786317967ff9bbe1ef2ea1293dda
Author: Peter Xu <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
M accel/kvm/trace-events
M include/sysemu/kvm_int.h
Log Message:
-----------
KVM: Dynamic sized kvm memslots array
Zhiyi reported an infinite loop issue in VFIO use case. The cause of that
was a separate discussion, however during that I found a regression of
dirty sync slowness when profiling.
Each KVMMemoryListerner maintains an array of kvm memslots. Currently it's
statically allocated to be the max supported by the kernel. However after
Linux commit 4fc096a99e ("KVM: Raise the maximum number of user memslots"),
the max supported memslots reported now grows to some number large enough
so that it may not be wise to always statically allocate with the max
reported.
What's worse, QEMU kvm code still walks all the allocated memslots entries
to do any form of lookups. It can drastically slow down all memslot
operations because each of such loop can run over 32K times on the new
kernels.
Fix this issue by making the memslots to be allocated dynamically.
Here the initial size was set to 16 because it should cover the basic VM
usages, so that the hope is the majority VM use case may not even need to
grow at all (e.g. if one starts a VM with ./qemu-system-x86_64 by default
it'll consume 9 memslots), however not too large to waste memory.
There can also be even better way to address this, but so far this is the
simplest and should be already better even than before we grow the max
supported memslots. For example, in the case of above issue when VFIO was
attached on a 32GB system, there are only ~10 memslots used. So it could
be good enough as of now.
In the above VFIO context, measurement shows that the precopy dirty sync
shrinked from ~86ms to ~3ms after this patch applied. It should also apply
to any KVM enabled VM even without VFIO.
NOTE: we don't have a FIXES tag for this patch because there's no real
commit that regressed this in QEMU. Such behavior existed for a long time,
but only start to be a problem when the kernel reports very large
nr_slots_max value. However that's pretty common now (the kernel change
was merged in 2021) so we attached cc:stable because we'll want this change
to be backported to stable branches.
Cc: qemu-stable <[email protected]>
Reported-by: Zhiyi Guo <[email protected]>
Tested-by: Zhiyi Guo <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
Acked-by: David Hildenbrand <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 655f9c490e2095e99cd401ccdc163849c2b0bc0a
https://github.com/qemu/qemu/commit/655f9c490e2095e99cd401ccdc163849c2b0bc0a
Author: Peter Xu <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT
Make the default max nr_slots a macro, it's only used when KVM reports
nothing.
Reviewed-by: David Hildenbrand <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 3495d6eebcfaf82cae2fd9649dc9580afee7347f
https://github.com/qemu/qemu/commit/3495d6eebcfaf82cae2fd9649dc9580afee7347f
Author: Peter Xu <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
M include/sysemu/kvm_int.h
Log Message:
-----------
KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used
This will make all nr_slots counters to be named in the same manner.
Reviewed-by: David Hildenbrand <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 8f89bab523b9a9063a899892744d34e626886e62
https://github.com/qemu/qemu/commit/8f89bab523b9a9063a899892744d34e626886e62
Author: Peter Xu <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
M include/sysemu/kvm_int.h
Log Message:
-----------
KVM: Rename KVMState->nr_slots to nr_slots_max
This value used to reflect the maximum supported memslots from KVM kernel.
Rename it to be clearer.
Reviewed-by: David Hildenbrand <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: bf0a038bb41df0a098163b871ac58ad57493c50f
https://github.com/qemu/qemu/commit/bf0a038bb41df0a098163b871ac58ad57493c50f
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/seg_helper.c
Log Message:
-----------
target/i386/tcg: Use DPL-level accesses for interrupts and call gates
Stack accesses should be explicit and use the privilege level of the
target stack. This ensures that SMAP is not applied when the target
stack is in ring 3.
This fixes a bug wherein i386/tcg assumed that an interrupt return, or a
far call using the CALL or JMP instruction, was always going from kernel
or user mode to kernel mode when using a call gate. This assumption is
violated if the call gate has a DPL that is greater than 0.
Analyzed-by: Robert R. Henry <[email protected]>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/249
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: fdfd13c2ab0b782c0ea71ec03b808c311be5b513
https://github.com/qemu/qemu/commit/fdfd13c2ab0b782c0ea71ec03b808c311be5b513
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm
KVM_CAP_MULTI_ADDRESS_SPACE used to be a global capability, but with the
introduction of AMD SEV-SNP confidential VMs, the number of address spaces
can vary by VM type.
Query the extension on the VM level instead of on the KVM level.
Inspired by an analogous patch by Tom Dohrmann.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 13a0e5889d7167478195331c67cdd565b3539110
https://github.com/qemu/qemu/commit/13a0e5889d7167478195331c67cdd565b3539110
Author: Paolo Bonzini <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm
The exact set of available memory attributes can vary by VM. In the
future it might vary depending on enabled capabilities, too. Query the
extension on the VM level instead of on the KVM level, and only after
architecture-specific initialization.
Inspired by an analogous patch by Tom Dohrmann.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a50dd4e9a055b6fb7dbc4a442fe625a6c01c5972
https://github.com/qemu/qemu/commit/a50dd4e9a055b6fb7dbc4a442fe625a6c01c5972
Author: Tom Dohrmann <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: check for KVM_CAP_READONLY_MEM on VM
KVM_CAP_READONLY_MEM used to be a global capability, but with the
introduction of AMD SEV-SNP confidential VMs, this extension is not
always available on all VM types [1,2].
Query the extension on the VM level instead of on the KVM level.
[1]
https://patchwork.kernel.org/project/kvm/patch/[email protected]/
[2]
https://patchwork.kernel.org/project/kvm/patch/[email protected]/
Cc: Paolo Bonzini <[email protected]>
Signed-off-by: Tom Dohrmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4bfdcb24fa5dc0844d0e4ab2cebb6687a233c0ff
https://github.com/qemu/qemu/commit/4bfdcb24fa5dc0844d0e4ab2cebb6687a233c0ff
Author: Richard Henderson <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M target/i386/tcg/decode-new.c.inc
Log Message:
-----------
target/i386: Use only 16 and 32-bit operands for IN/OUT
The REX.W prefix is ignored for these instructions.
Mirror the solution already used for INS/OUTS: X86_SIZE_z.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2581
Signed-off-by: Richard Henderson <[email protected]>
Cc: [email protected]
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f5b2e850b95ea806f4ee1bffac7b452ae23ac93a
https://github.com/qemu/qemu/commit/f5b2e850b95ea806f4ee1bffac7b452ae23ac93a
Author: Peter Maydell <[email protected]>
Date: 2024-10-15 (Tue, 15 Oct 2024)
Changed paths:
M accel/kvm/kvm-all.c
M accel/kvm/trace-events
M docs/system/i386/hyperv.rst
M include/sysemu/kvm_int.h
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv.c
M target/i386/kvm/kvm.c
M target/i386/machine.c
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/seg_helper.c
M target/i386/tcg/translate.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: Fixes for IN and OUT with REX prefix
* target/i386: New CPUID features and logic fixes
* target/i386: Add support save/load HWCR MSR
* target/i386: Move more instructions to new decoder; separate decoding
and IR generation
* target/i386/tcg: Use DPL-level accesses for interrupts and call gates
* accel/kvm: perform capability checks on VM file descriptor when necessary
* accel/kvm: dynamically sized kvm memslots array
* target/i386: fixes for Hyper-V
* docs/system: Add recommendations to Hyper-V enlightenments doc
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# gpg: Signature made Tue 15 Oct 2024 15:15:58 BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [full]
# gpg: aka "Paolo Bonzini <[email protected]>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (25 commits)
target/i386: Use only 16 and 32-bit operands for IN/OUT
accel/kvm: check for KVM_CAP_READONLY_MEM on VM
accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm
accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm
target/i386/tcg: Use DPL-level accesses for interrupts and call gates
KVM: Rename KVMState->nr_slots to nr_slots_max
KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used
KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT
KVM: Dynamic sized kvm memslots array
target/i386: assert that cc_op* and pc_save are preserved
target/i386: list instructions still in translate.c
target/i386: do not check PREFIX_LOCK in old-style decoder
target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder
target/i386: decode address before going back to translate.c
target/i386: convert bit test instructions to new decoder
docs/system: Add recommendations to Hyper-V enlightenments doc
target/i386: Make sure SynIC state is really updated before KVM_RUN
target/i386: Exclude 'hv-syndbg' from 'hv-passthrough'
target/i386: Fix conditional CONFIG_SYNDBG enablement
target/i386: Add support save/load HWCR MSR
...
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/f774a6775079...f5b2e850b95e
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