Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3b5948f808e3b99aedfa0aff45cffbe8b7ec07ed
https://github.com/qemu/qemu/commit/3b5948f808e3b99aedfa0aff45cffbe8b7ec07ed
Author: Avihai Horon <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/vfio/migration.c
Log Message:
-----------
vfio/migration: Report only stop-copy size in vfio_state_pending_exact()
vfio_state_pending_exact() is used to update migration core how much
device data is left for the device migration. Currently, the sum of
pre-copy and stop-copy sizes of the VFIO device are reported.
The pre-copy size is obtained via the VFIO_MIG_GET_PRECOPY_INFO ioctl,
which returns the amount of device data available to be transferred
while the device is in the PRE_COPY states.
The stop-copy size is obtained via the VFIO_DEVICE_FEATURE_MIG_DATA_SIZE
ioctl, which returns the total amount of device data left to be
transferred in order to complete the device migration.
According to the above, current implementation is wrong -- it reports
extra overlapping data because pre-copy size is already contained in
stop-copy size. Fix it by reporting only stop-copy size.
Fixes: eda7362af959 ("vfio/migration: Add VFIO migration pre-copy support")
Signed-off-by: Avihai Horon <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: fa4e20defe239e42af0a1b5c030dec114f799f56
https://github.com/qemu/qemu/commit/fa4e20defe239e42af0a1b5c030dec114f799f56
Author: Avihai Horon <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/vfio/trace-events
Log Message:
-----------
vfio/migration: Change trace formats from hex to decimal
Data sizes in VFIO migration trace events are printed in hex format
while in migration core trace events they are printed in decimal format.
This inconsistency makes it less readable when using both trace event
types. Hence, change the data sizes print format to decimal in VFIO
migration trace events.
Signed-off-by: Avihai Horon <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 49915c0d2c9868e6f25e52e4d839943611b69e98
https://github.com/qemu/qemu/commit/49915c0d2c9868e6f25e52e4d839943611b69e98
Author: Alex Williamson <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/vfio/helpers.c
Log Message:
-----------
vfio/helpers: Refactor vfio_region_mmap() error handling
Move error handling code to the end of the function so that it can more
easily be shared by new mmap failure conditions. No functional change
intended.
Signed-off-by: Alex Williamson <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 00b519c0bca0e933ed22e2e6f8bca6b23f41f950
https://github.com/qemu/qemu/commit/00b519c0bca0e933ed22e2e6f8bca6b23f41f950
Author: Alex Williamson <[email protected]>
Date: 2024-10-23 (Wed, 23 Oct 2024)
Changed paths:
M hw/vfio/helpers.c
Log Message:
-----------
vfio/helpers: Align mmaps
Thanks to work by Peter Xu, support is introduced in Linux v6.12 to
allow pfnmap insertions at PMD and PUD levels of the page table. This
means that provided a properly aligned mmap, the vfio driver is able
to map MMIO at significantly larger intervals than PAGE_SIZE. For
example on x86_64 (the only architecture currently supporting huge
pfnmaps for PUD), rather than 4KiB mappings, we can map device MMIO
using 2MiB and even 1GiB page table entries.
Typically mmap will already provide PMD aligned mappings, so devices
with moderately sized MMIO ranges, even GPUs with standard 256MiB BARs,
will already take advantage of this support. However in order to better
support devices exposing multi-GiB MMIO, such as 3D accelerators or GPUs
with resizable BARs enabled, we need to manually align the mmap.
There doesn't seem to be a way for userspace to easily learn about PMD
and PUD mapping level sizes, therefore this takes the simple approach
to align the mapping to the power-of-two size of the region, up to 1GiB,
which is currently the maximum alignment we care about.
Cc: Peter Xu <[email protected]>
Signed-off-by: Alex Williamson <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 33343bff71805fbcb155abbb112a6e9154335c89
https://github.com/qemu/qemu/commit/33343bff71805fbcb155abbb112a6e9154335c89
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio/aspeed: Fix coding style
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 9422dbd10b759a558de8b620ade4686d407fc63f
https://github.com/qemu/qemu/commit/9422dbd10b759a558de8b620ade4686d407fc63f
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio/aspeed: Support to set the different memory size
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of
register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of
register space for AST2600 1.8v and owns 2KB of register space for
AST2600 3.3v.
It set the memory region size 2KB by default and it does not compatible
register space for AST2700.
Introduce a new class attribute to set the GPIO controller memory size
for different ASPEED SOCs.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 404e75343c3faef7d8e042dd3ad3153a9815ade1
https://github.com/qemu/qemu/commit/404e75343c3faef7d8e042dd3ad3153a9815ade1
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio/aspeed: Support different memory region ops
It set "aspeed_gpio_ops" struct which containing read and write callbacks
to be used when I/O is performed on the GPIO region.
Besides, in the previous design of ASPEED SOCs, one register is used for
setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600.
ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600.
However, the register set have a significant change in AST2700.
Each GPIO pin has their own control register. In other words, users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on
in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and
use it in aspeed_gpio_realize function.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 7e22f6fafef951b336d1427d781d2e4a71f37d9f
https://github.com/qemu/qemu/commit/7e22f6fafef951b336d1427d781d2e4a71f37d9f
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode
The interrupt status field is W1C, where a set bit on read indicates an
interrupt is pending. If the bit extracted from data is set it should
clear the corresponding bit in reg_value. However, if the extracted
bit is clear then the value of the corresponding bit in reg_value
should be unchanged.
SHARED_FIELD_EX32() extracts the interrupt status bit from the write
(data). reg_value is set to the set's interrupt status, which means
that for any pin with an interrupt pending, the corresponding bit is
set. The deposit32() call updates the bit at pin_idx in the
reg_value, using the value extracted from the write (data).
The result is that if multiple interrupt status bits
were pending and the write was acknowledging specific one bit,
then the all interrupt status bits will be cleared.
However, it is index mode and should only clear the corresponding bit.
For example, say we have an interrupt pending for GPIOA0, where the
following statements are true:
set->int_status == 0b01
s->pending == 1
Before it is acknowledged, an interrupt becomes pending for GPIOA1:
set->int_status == 0b11
s->pending == 2
A write is issued to acknowledge the interrupt for GPIOA0. This causes
the following sequence:
reg_value == 0b11
pending == 2
s->pending == 0
set->int_status == 0b00
It should only clear bit 0 in index mode and the correct result
should be as following.
set->int_status == 0b11
s->pending == 2
pending == 1
s->pending == 1
set->int_status == 0b10
Signed-off-by: Jamin Lin <[email protected]>
Suggested-by: Andrew Jeffery <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Commit: bac698832de3160e3327a007a86958be08ecbd35
https://github.com/qemu/qemu/commit/bac698832de3160e3327a007a86958be08ecbd35
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw/gpio/aspeed: Add AST2700 support
AST2700 integrates two set of Parallel GPIO Controller with maximum 212
control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs, one register is used for setting
one function for one set which are 32 pins and 4 groups.
ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600.
ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600.
However, the register set have a significant change since AST2700.
Each GPIO pin has their own individual control register.
In other words, users are able to set one GPIO pin’s direction,
interrupt enable, input mask and so on in the same one register.
Currently, aspeed_gpio_read and aspeed_gpio_write callback functions
are not compatible AST2700.
Introduce new aspeed_gpio_2700_read and aspeed_gpio_2700_write callback
functions and aspeed_gpio_2700_ops memory region operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Commit: f34030ec7e2672d811bf60e2922f8487d74e3980
https://github.com/qemu/qemu/commit/f34030ec7e2672d811bf60e2922f8487d74e3980
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
aspeed/soc: Correct GPIO irq 130 for AST2700
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO 1.8v, removes
ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO
device in AST2700.
The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at
bit 18. Therefore, correct GPIO irq 130.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: c6a8a2a7e93a0e656c046d945962468f96aa9b4c
https://github.com/qemu/qemu/commit/c6a8a2a7e93a0e656c046d945962468f96aa9b4c
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
aspeed/soc: Support GPIO for AST2700
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 34fdd734c5da7de39c09f3d8793042292f95dacc
https://github.com/qemu/qemu/commit/34fdd734c5da7de39c09f3d8793042292f95dacc
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M MAINTAINERS
A tests/qtest/ast2700-gpio-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700
Add GPIO test cases to test output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
[ clg: - Updated MAINTAINERS ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 4c1d0af4a28d15d04a9bd522a5c3976eda9f999e
https://github.com/qemu/qemu/commit/4c1d0af4a28d15d04a9bd522a5c3976eda9f999e
Author: Alejandro Zeise <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Fix SG Accumulative hashing
Make the Aspeed HACE module use the new qcrypto accumulative hashing functions
when in scatter-gather accumulative mode. A hash context will maintain a
"running-hash" as each scatter-gather chunk is received.
Previously each scatter-gather "chunk" was cached
so the hash could be computed once the final chunk was received.
However, the cache was a shallow copy, so once the guest overwrote the
memory provided to HACE the final hash would not be correct.
Possibly related to: https://gitlab.com/qemu-project/qemu/-/issues/1121
Buglink: https://github.com/openbmc/qemu/issues/36
Signed-off-by: Alejandro Zeise <[email protected]>
[ clg: - Checkpatch fixes
- Reworked qcrypto_hash*() error reports in do_hash_operation() ]
Signed-off-by: Cédric Le Goater <[email protected]>
Acked-by: Andrew Jeffery <[email protected]>
Reviewed-by: Jamin Lin <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Commit: f04cb2d00d5cc3ecc32cd129676fe221233345f9
https://github.com/qemu/qemu/commit/f04cb2d00d5cc3ecc32cd129676fe221233345f9
Author: Cédric Le Goater <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M tests/avocado/machine_aspeed.py
M tests/functional/meson.build
A tests/functional/test_arm_aspeed.py
Log Message:
-----------
tests/functional: Convert most Aspeed machine tests
This is a simple conversion of the tests with some cleanups and
adjustments to match the new test framework. Replace the zephyr image
MD5 hashes with SHA256 hashes while at it.
The SDK tests depend on a ssh class from avocado.utils which is
difficult to replace. To be addressed separately.
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Commit: 05d501a1ea13d395baba7abd0e1436b0c4ed073f
https://github.com/qemu/qemu/commit/05d501a1ea13d395baba7abd0e1436b0c4ed073f
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Fix write incorrect data into flash in user mode
According to the design of ASPEED SPI controllers user mode, users write the
data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1
enter user mode. Then, SPI drivers send flash commands for writing data.
Finally, SPI drivers set the Control Register (0x10) bit 2 to stop
active control and restore bit 0 and 1.
According to the design of ASPEED SMC model, firmware writes the
Control Register and the "aspeed_smc_flash_update_ctrl" function is called.
Then, this function verify Control Register(0x10) bit 0 and 1. If it set user
mode, the value of s->snoop_index is SNOOP_START else SNOOP_OFF.
If s->snoop_index is SNOOP_START, the "aspeed_smc_do_snoop" function verify
the first incomming data is a new flash command and writes the corresponding
dummy bytes if need.
However, it did not check the current unselect status. If current unselect
status is "false" and firmware set the IO MODE by Control Register bit 31:28,
the value of s->snoop_index will be changed to SNOOP_START again and
"aspeed_smc_do_snoop" misunderstand that the incomming data is the new flash
command and it causes writing unexpected data into flash.
Example:
1. Firmware set user mode by Control Register bit 0 and 1(0x03)
2. SMC model set s->snoop SNOOP_START
3. Firmware set Quad Page Program with 4-Byte Address command (0x34)
4. SMC model verify this flash command and it needs 4 dummy bytes.
5. Firmware send 4 bytes address.
6. SMC model receives 4 bytes address
7. Firmware set QPI IO MODE by Control Register bit 31. (0x80000003)
8. SMC model verify new user mode by Control Register bit 0 and 1.
Then, set s->snoop SNOOP_START again. (It is the wrong behavior.)
9. Firmware send 0xebd8c134 data and it should be written into flash.
However, SMC model misunderstand that the first incoming data, 0x34,
is the new command because the value of s->snoop is changed to SNOOP_START.
Finally, SMC sned the incorrect data to flash model.
Introduce a new unselect attribute in AspeedSMCState to save the current
unselect status for user mode and set it "true" by default.
Update "aspeed_smc_flash_update_ctrl" function to check the previous unselect
status. If both new unselect status and previous unselect status is different,
update s->snoop_index value and call "aspeed_smc_flash_do_select".
Increase VMStateDescription version.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[ clg: - Replaced VMSTATE_BOOL -> VMSTATE_BOOL_V ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c0400e3ac6c2d5751ce2bff314f3cc7a01e7c50d
https://github.com/qemu/qemu/commit/c0400e3ac6c2d5751ce2bff314f3cc7a01e7c50d
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw/block:m25p80: Fix coding style
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 9785731ec4f7f314d583e65114da5afd90980420
https://github.com/qemu/qemu/commit/9785731ec4f7f314d583e65114da5afd90980420
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq
According to the w25q01jv datasheet at page 16, it is required to set QE bit
in "Status Register 2" to enable quad mode.
Currently, m25p80 support users utilize "Write Status Register 1(0x01)" command
to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)"
command to get the QE bit status.
However, some firmware directly utilize "Status Register 2(0x31)" command to
set QE bit. To fully support quad mode for w25q01jvq, adds WRSR2 command.
Update collecting data needed 1 byte for WRSR2 command in decode_new_cmd
function and verify QE bit at the first byte of collecting data bit 2 in
complete_collecting_data.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 146f078a6375f06d811a174ffe8e1c119bf907fd
https://github.com/qemu/qemu/commit/146f078a6375f06d811a174ffe8e1c119bf907fd
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
hw/block/m25p80: Add SFDP table for w25q80bl flash
Add the SFDP table for the Windbond w25q80bl flash.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: a37bbfbb18593483cbcf9d194049dbb2ca3e6e90
https://github.com/qemu/qemu/commit/a37bbfbb18593483cbcf9d194049dbb2ca3e6e90
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.
Currently, the default spi_model was "sst25vf032b" whose size was 4MB for
ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB,
ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size
was 32MB.
Correct spi_model default flash to w25q256 for ast1030-a1 EVB.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: e15001bc804f811343e4984d55f90fe70029598a
https://github.com/qemu/qemu/commit/e15001bc804f811343e4984d55f90fe70029598a
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB
Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for
ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB,
ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and
"w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256
is 32MB.
The fmc_cs0 was connected to AST1030 A1 internal flash and the fmc_cs1 was
connected to external flash. The internal flash could not be changed because
it was placed into AST1030 A1 chip. Users only can change fmc_cs1 external
flash.
So far, only supports to set the default fmc_model for all chip select pins.
In other words, users cannot set the different default flash model for
fmc_cs0 and fmc_cs1, respectively.
Correct fmc_model default flash to w25q80bl the same as AST1030 A1
internal flash for ast1030-a1 EVB.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 1df52a9ac0897687cff7c38705007b2b58065042
https://github.com/qemu/qemu/commit/1df52a9ac0897687cff7c38705007b2b58065042
Author: Jamin Lin <[email protected]>
Date: 2024-10-24 (Thu, 24 Oct 2024)
Changed paths:
M tests/qtest/aspeed_smc-test.c
Log Message:
-----------
test/qtest/aspeed_smc-test: Fix coding style
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Commit: 94be8fd6926cb20c1aa8dd361c6bc10b39b9a376
https://github.com/qemu/qemu/commit/94be8fd6926cb20c1aa8dd361c6bc10b39b9a376
Author: Peter Maydell <[email protected]>
Date: 2024-10-25 (Fri, 25 Oct 2024)
Changed paths:
M hw/vfio/helpers.c
M hw/vfio/migration.c
M hw/vfio/trace-events
Log Message:
-----------
Merge tag 'pull-vfio-20241024' of https://github.com/legoater/qemu into
staging
vfio queue:
* Fixed size reported in vfio_state_pending_exact()
* Added support for PMD or PUD aligned mappings
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ22wACgkQUaNDx8/7
# 7KHU5g/8Cr1487IJQb5cbpLu2Nviu3wjzhbCFFdbl99uLifdc0GK1P6fqDNQ7BVx
# 2vpZgJRXLTxlUSTpreFw4z6TH7/C4HoNiluQV4l0vxqG/Y9q68SJBpT9WENwXUyY
# +2laDmGQbUjDznxIFlmCgZZAssCIJNp0esNE9hvwkQCarZx9m+QQSSkeVHVWNFqX
# +zTd4v076Q9hi53+4e7FlqFKaFoa54IcZe3gz+GjY/IXMqCDNFw9e9xJxML+zSg3
# HZ4/YMQj+EsKX2gm460EYBmt13kd0wdtFzA1MNc7XcSlBlLk/WmezpEzHZRubiLs
# mbUZ68/cweJmrO0WatycWg9JwQ2q9FlKH1Acgun4Fcf8Zov5ovHuYAsWYbdGDbN1
# E7pY/XlUf6b7Vk+yAGTnKKRi6OguTEmVyRRFy/4V8TwvZNycbeOMebKilGQUGfKj
# iLWuzF6NilT4ZGo7sWnlLZWcmrxN57wJh77GlmcqiqguskB8WGdh/SZSVCkkzr3y
# PN3FGSTseNaxalcjECEFnfE8+bUShLei+I6fppTfqLBaLHJ72lRel0Cg07FS8oM4
# 3ev7etH7jFT5xET00DBamDXacgNtLqFqO6XIK3bFTkLmP0FFQi9u+bvy04IyTVCC
# gd9Zg2vhxp0mjuwtelB+i7yD3pmA2LWFkEzoShpkH/h38CnpoyQ=
# =+69I
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Oct 2024 06:30:20 BST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20241024' of https://github.com/legoater/qemu:
vfio/helpers: Align mmaps
vfio/helpers: Refactor vfio_region_mmap() error handling
vfio/migration: Change trace formats from hex to decimal
vfio/migration: Report only stop-copy size in vfio_state_pending_exact()
Signed-off-by: Peter Maydell <[email protected]>
Commit: cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2
https://github.com/qemu/qemu/commit/cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2
Author: Peter Maydell <[email protected]>
Date: 2024-10-25 (Fri, 25 Oct 2024)
Changed paths:
M MAINTAINERS
M hw/arm/aspeed.c
M hw/arm/aspeed_ast27x0.c
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
M hw/gpio/aspeed_gpio.c
M hw/misc/aspeed_hace.c
M hw/ssi/aspeed_smc.c
M include/hw/gpio/aspeed_gpio.h
M include/hw/misc/aspeed_hace.h
M include/hw/ssi/aspeed_smc.h
M tests/avocado/machine_aspeed.py
M tests/functional/meson.build
A tests/functional/test_arm_aspeed.py
M tests/qtest/aspeed_smc-test.c
A tests/qtest/ast2700-gpio-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Fixed GPIO interrupt status when in index mode
* Added GPIO support for the AST2700 SoC and specific test cases
* Fixed crypto controller (HACE) Accumulative hash function
* Converted Aspeed machine avocado tests to the new functional
framework. SDK tests still to be addressed.
* Fixed issue in the SSI controller when doing writes in user mode
* Added support for the WRSR2 register of Winbond flash devices
* Added SFDP table for the Windbond w25q80bl flash device
* Changed flash device models for the ast1030-a1 EVB
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ6MIACgkQUaNDx8/7
# 7KFQPA//RTxi1PmCDlzd1ffzMWEadD3CpGLJ4RgEeZpNtkx6IF2uFFBdlNgjTSmD
# B8FdIOVb8qo2omXahKIVIgoKbGgn3U3jciH67D/x4Jyp8IhW6n5XwZzKNJ7kLVHX
# IluGmlvqNumSKl3vxsLvprC0ojRiO/SfWkzS6VOwoFPM7uNDTybQicWBBoy3Jh3e
# VVlMwIeKHMQVJGpI8PQbtnFZO4HaMqWwlo0EoIJji59fdyWULLvrXzH9YhzwFVjQ
# oCNvJUBLfxLse7c13cm/LuNmw+IQtLC5OztsOOtv1XZ1MruhJ7t316eGsQEpeWcD
# Yy5RK4mIBJMExu9oxcKOqgSznQSgenvNGWg6Z9FyyKGciylafnE8GeT35WObumyD
# v9gzgeLcw5DgvDgQXaYi4IkKyezaHoE3HPbFdBEZHBt8tn5pPGmXM0lEWL5xQ5B8
# h6HphjxIlFxeHIxYenLJowLBMOt8aFXzGboF2XCLrx19OC2zvoo7klCbFeAfZpvQ
# JMXP+GsQIe7fnBMbyXGrJh9q+/7tKR4ivtTV/vnSF0FPtyzxdoSrYsUA4SZqSWvI
# ONz62p+zlE/oXBUIaFnC2Ea41YwJ7mDbmcSU1dFxmE0xRVmoYlUocoeS2VOUmTH0
# CMgEcmMXQG0vx8nipQbScbuWRCBlf0YwJ7Y7stgI8HabmsMMbIg=
# =DqCH
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Oct 2024 07:27:14 BST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu:
test/qtest/aspeed_smc-test: Fix coding style
hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB
hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.
hw/block/m25p80: Add SFDP table for w25q80bl flash
hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq
hw/block:m25p80: Fix coding style
aspeed/smc: Fix write incorrect data into flash in user mode
tests/functional: Convert most Aspeed machine tests
hw/misc/aspeed_hace: Fix SG Accumulative hashing
tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700
aspeed/soc: Support GPIO for AST2700
aspeed/soc: Correct GPIO irq 130 for AST2700
hw/gpio/aspeed: Add AST2700 support
hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Fix coding style
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/e17e57e862fa...cea8ac78545a
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications
