Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 5979f50fa9fdbb3fb49e2b498f84faa7503c8ed1
https://github.com/qemu/qemu/commit/5979f50fa9fdbb3fb49e2b498f84faa7503c8ed1
Author: Xiaoyao Li <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported
Since commit c6bd2dd63420 ("i386/cpu: Set up CPUID_HT in
x86_cpu_expand_features() instead of cpu_x86_cpuid()") and
commit 99a637a86f55 ("i386/cpu: Set and track CPUID_EXT3_CMP_LEG in
env->features[FEAT_8000_0001_ECX]"), it gets warnings when booting the
VM with vcpus >= 2 and with tcg:
qemu-system-x86_64: warning: TCG doesn't support requested feature:
CPUID.01H:EDX.ht [bit 28]
qemu-system-x86_64: warning: TCG doesn't support requested feature:
CPUID.80000001H:ECX.cmp-legacy [bit 1]
This is because, after the two commits, CPUID_HT and CPUID_EXT3_CMP_LEG
are set in env->features[] when vcpus >=2 (in x86_cpu_expand_features())
later in x86_cpu_filter_features() it will check against the TCG supported
bits. However, current TCG doesn't mark the two bits as supported, hence
the warnings.
Fix it by adding the two bits to the supported bits of TCG since multiple
vcpus are supported by TCG.
Fixes: c6bd2dd63420 ("i386/cpu: Set up CPUID_HT in x86_cpu_expand_features()
instead of cpu_x86_cpuid()")
Fixes: 99a637a86f55 ("i386/cpu: Set and track CPUID_EXT3_CMP_LEG in
env->features[FEAT_8000_0001_ECX]")
Reported-by: Ewan Hai <[email protected]>
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7a48612306768833f8cc87418a5a53e712f26ac1
https://github.com/qemu/qemu/commit/7a48612306768833f8cc87418a5a53e712f26ac1
Author: Xiaoyao Li <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/i386/hvf/x86_cpuid.c
Log Message:
-----------
i386/hvf: Make CPUID_HT supported
Since Commit c6bd2dd63420 ("i386/cpu: Set up CPUID_HT in
x86_cpu_expand_features() instead of cpu_x86_cpuid()"), CPUID_HT will be
set in env->features[] in x86_cpu_expand_features() when vcpus >= 2.
Later in x86_cpu_filter_features() it will check against the HVF
supported bits. It will trigger the warning like
qemu-system-x86_64: warning: host doesn't support requested feature:
CPUID.01H:EDX.ht [bit 28]
Add CPUID_HT to HVF supported CPUID bits to fix it.
Signed-off-by: Xiaoyao Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e5894fd6f411c113e2b5f62811e96eeb5b084381
https://github.com/qemu/qemu/commit/e5894fd6f411c113e2b5f62811e96eeb5b084381
Author: Rakesh Jeyasingh <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/pci-host/gt64120.c
Log Message:
-----------
hw/pci-host/gt64120: Fix endianness handling
The GT-64120 PCI controller requires special handling where:
1. Host bridge(bus 0 ,device 0) must never be byte-swapped
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
The previous implementation incorrectly swapped all accesses, breaking
host bridge detection (lspci -d 11ab:4620).
Changes made:
1. Removed gt64120_update_pci_cfgdata_mapping() and moved data_mem
initialization
to gt64120_realize() for cleaner setup
2. Implemented custom read/write handlers that:
- Preserve host bridge accesses (extract32(config_reg,11,13)==0)
- apply swapping only for non-bridge devices in big-endian mode
Fixes: 145e2198 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2826
Signed-off-by: Rakesh Jeyasingh <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 560375cff3ccedabf1fe5ca1bc7a31b13fdc68e5
https://github.com/qemu/qemu/commit/560375cff3ccedabf1fe5ca1bc7a31b13fdc68e5
Author: Rakesh Jeyasingh <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/pci/pci_host.c
M include/hw/pci-host/dino.h
M include/hw/pci/pci_host.h
Log Message:
-----------
hw/pci-host: Remove unused pci_host_data_be_ops
pci_host_data_be_ops became unused after endianness fixes
Suggested-by: Paolo Bonzini <[email protected]>
Signed-off-by: Rakesh Jeyasingh <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a1b3e82773c4b9f438c2d77f9101fca760b347e6
https://github.com/qemu/qemu/commit/a1b3e82773c4b9f438c2d77f9101fca760b347e6
Author: Zhao Liu <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/i386/sgx.c
M qapi/misc-target.json
Log Message:
-----------
qapi/misc-target: Rename SGXEPCSection to SgxEpcSection
QAPI requires strict PascalCase naming style, i.e., only the first
letter of a single word is allowed to be uppercase, which could help
with readability.
Rename SGXEPCSection to SgxEpcSection.
Signed-off-by: Zhao Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 88aea26d1880f105b00c352485d3bf1f21d55012
https://github.com/qemu/qemu/commit/88aea26d1880f105b00c352485d3bf1f21d55012
Author: Zhao Liu <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/i386/sgx-stub.c
M hw/i386/sgx.c
M qapi/misc-target.json
Log Message:
-----------
qapi/misc-target: Rename SGXInfo to SgxInfo
QAPI requires strict PascalCase naming style, i.e., only the first
letter of a single word is allowed to be uppercase, which could help
with readability.
Rename SGXInfo to SgxInfo.
Signed-off-by: Zhao Liu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: c6b8fb0fb1599cffdfe6603f93bba937c1ecb0b1
https://github.com/qemu/qemu/commit/c6b8fb0fb1599cffdfe6603f93bba937c1ecb0b1
Author: Zhao Liu <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M qapi/misc-target.json
Log Message:
-----------
qapi/misc-target: Fix the doc related SGXEPCSection
The "sections" field of SGXInfo is used to gather EPC section
information for both the guest and the host. Therefore, delete the "for
guest" limitation.
Additionally, avoid the abbreviation "info" and use "information"
instead. And for SGXEPCSection, delete the redundant word "info".
Reported-by: Markus Armbruster <[email protected]>
Signed-off-by: Zhao Liu <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7f2131c35c1781ca41c62dc26fd93282e1351323
https://github.com/qemu/qemu/commit/7f2131c35c1781ca41c62dc26fd93282e1351323
Author: Zhao Liu <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M qapi/misc-target.json
Log Message:
-----------
qapi/misc-target: Fix the doc to distinguish query-sgx and
query-sgx-capabilities
There're 2 QMP commands: query-sgx and query-sgx-capabilities, but
their outputs are very similar and the documentation lacks clear
differentiation.
>From the codes, query-sgx is used to gather guest's SGX capabilities
(including SGX related CPUIDs and EPC sections' size, in SGXInfo), and
if guest doesn't have SGX, then QEMU will report the error message.
On the other hand, query-sgx-capabilities is used to gather host's SGX
capabilities (descripted by SGXInfo as well). And if host doesn't
support SGX, then QEMU will also report the error message.
Considering that SGXInfo is already documented and both these 2 commands
have enough error messages (for the exception case in their codes).
Therefore the QAPI documentation for these two commands only needs to
emphasize that one of them applies to the guest and the other to the
host.
Fix their documentation to reflect this difference.
Reported-by: Markus Armbruster <[email protected]>
Suggested-by: Paolo Bonzini <[email protected]>
Signed-off-by: Zhao Liu <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 82c81c07e83670befc61333e0bdf3d810e581219
https://github.com/qemu/qemu/commit/82c81c07e83670befc61333e0bdf3d810e581219
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/riscv/virt-acpi-build.c
Log Message:
-----------
hw/riscv: acpi: only create RHCT MMU entry for supported types
Do not create the RHCT MMU type entry for RV32 CPUs, since it
only has definitions for SV39/SV48/SV57. Likewise, check that
satp_mode_max_from_map() will actually return a valid value, skipping
the MMU type entry if all MMU types were disabled on the command line.
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b22cfa0f44e360d09595705cea8c97be692e2080
https://github.com/qemu/qemu/commit/b22cfa0f44e360d09595705cea8c97be692e2080
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: assert argument to set_satp_mode_max_supported is valid
Check that the argument to set_satp_mode_max_supported is valid for
the MXL value of the CPU. It would be a bug in the CPU definition
if it weren't.
In fact, there is such a bug in riscv_bare_cpu_init(): not just
SV64 is not a valid VM mode for 32-bit CPUs, SV64 is not a
valid VM mode at all, not yet at least.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 357ce8171a9c7581ba02475874c8c28ed5220d9e
https://github.com/qemu/qemu/commit/357ce8171a9c7581ba02475874c8c28ed5220d9e
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: cpu: store max SATP mode as a single integer
The maximum available SATP mode implies all the shorter virtual address sizes.
Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_map.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 211c7f9bb817ca7bb7855535da4db5ca80a8aa1d
https://github.com/qemu/qemu/commit/211c7f9bb817ca7bb7855535da4db5ca80a8aa1d
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/riscv/virt-acpi-build.c
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: update max_satp_mode based on QOM properties
Almost all users of cpu->cfg.satp_mode care about the "max" value
satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM
properties back into it. For TCG, deduce the bitmap of supported modes
from valid_vm[].
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: dabb54c160b84d648f375d8f7688fb1099ba32ab
https://github.com/qemu/qemu/commit/dabb54c160b84d648f375d8f7688fb1099ba32ab
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: remove supported from RISCVSATPMap
"supported" can be computed on the fly based on the max_satp_mode.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 80b22be3820f1076d9de1b1f1646ae6b352d7675
https://github.com/qemu/qemu/commit/80b22be3820f1076d9de1b1f1646ae6b352d7675
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: move satp_mode.{map,init} out of CPUConfig
They are used to provide the nice QOM properties for svNN,
but the canonical source of the CPU configuration is now
cpu->cfg.max_satp_mode. Store them in the ArchCPU struct.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 71fb3aa5ebba5ba822371f864a12dbcded08147d
https://github.com/qemu/qemu/commit/71fb3aa5ebba5ba822371f864a12dbcded08147d
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: introduce RISCVCPUDef
Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4
https://github.com/qemu/qemu/commit/5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/riscv/boot.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: store RISCVCPUDef struct directly in the class
Prepare for adding more fields to RISCVCPUDef and reading them in
riscv_cpu_init: instead of storing the misa_mxl_max field in
RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
and go through it.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7f9e15d82d21714a2c82aff8869b8ef9aa191c98
https://github.com/qemu/qemu/commit/7f9e15d82d21714a2c82aff8869b8ef9aa191c98
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: merge riscv_cpu_class_init with the class_base function
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 12877e739b3afff2b6ff7b80d6a6b22e451671c2
https://github.com/qemu/qemu/commit/12877e739b3afff2b6ff7b80d6a6b22e451671c2
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu_cfg.h
A target/riscv/cpu_cfg_fields.h.inc
Log Message:
-----------
target/riscv: move RISCVCPUConfig fields to a header file
To support merging a subclass's RISCVCPUDef into the superclass, a list
of all the CPU features is needed. Put them into a header file that
can be included multiple times, expanding the macros BOOL_FIELD and
TYPE_FIELD to different operations.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 407254031edd649e6acde736e3f7e95bb0fdf299
https://github.com/qemu/qemu/commit/407254031edd649e6acde736e3f7e95bb0fdf299
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
Log Message:
-----------
target/riscv: include default value in cpu_cfg_fields.h.inc
In preparation for adding a function to merge two RISCVCPUConfigs
(pulling values from the parent if they are not overridden) annotate
cpu_cfg_fields.h.inc with the default value of the fields.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a6ba81424a7e751fbcee40dc1f5826ba29fddd30
https://github.com/qemu/qemu/commit/a6ba81424a7e751fbcee40dc1f5826ba29fddd30
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: add more RISCVCPUDef fields
Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
functions. To simulate inheritance, merge the child's RISCVCPUDef with
the parent and then finally move it to the CPUState at the end of
TYPE_RISCV_CPU's own instance_init function.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4e012d36c8654e7fa12762002150334bf591628a
https://github.com/qemu/qemu/commit/4e012d36c8654e7fa12762002150334bf591628a
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: convert abstract CPU classes to RISCVCPUDef
Start from the top of the hierarchy: dynamic and vendor CPUs are just
markers, whereas bare CPUs can have their instance_init function
replaced by RISCVCPUDef.
The only difference is that the maximum supported SATP mode has to
be specified separately for 32-bit and 64-bit modes.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 198265df8a71e6743d42d5003c29a060fea7d019
https://github.com/qemu/qemu/commit/198265df8a71e6743d42d5003c29a060fea7d019
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: convert profile CPU models to RISCVCPUDef
Profile CPUs reuse the instance_init function for bare CPUs; make them
proper subclasses instead. Enabling a profile is now done based on the
RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef,
subclasses check that the parent class's profile is enabled through the
parent profile mechanism.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 37815d80be11f98636a4ed76fe6b1ecc7aefcaf3
https://github.com/qemu/qemu/commit/37815d80be11f98636a4ed76fe6b1ecc7aefcaf3
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert bare CPU models to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0edc2465ba76c0d2bbeb475b6d2491c92dccd27b
https://github.com/qemu/qemu/commit/0edc2465ba76c0d2bbeb475b6d2491c92dccd27b
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert dynamic CPU models to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e89d4931d0a15ff0481e9a6e7cbb9f7a28e91434
https://github.com/qemu/qemu/commit/e89d4931d0a15ff0481e9a6e7cbb9f7a28e91434
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert SiFive E CPU models to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5106b8ee9ac78505f872a956c931c1f965ad073e
https://github.com/qemu/qemu/commit/5106b8ee9ac78505f872a956c931c1f965ad073e
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert ibex CPU models to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5a62948c91a910de4f9c7332cf8803152c099eac
https://github.com/qemu/qemu/commit/5a62948c91a910de4f9c7332cf8803152c099eac
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert SiFive U models to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1d84c2401c48617b8695d292602e2e777e0d1178
https://github.com/qemu/qemu/commit/1d84c2401c48617b8695d292602e2e777e0d1178
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/th_csr.c
Log Message:
-----------
target/riscv: th: make CSR insertion test a bit more intuitive
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int. Make the insertion_test
optional, too.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1016b0364f981e7aa9304866d7d756813e8dc6c2
https://github.com/qemu/qemu/commit/1016b0364f981e7aa9304866d7d756813e8dc6c2
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/th_csr.c
Log Message:
-----------
target/riscv: generalize custom CSR functionality
While at it, constify it so that the RISCVCSR array in RISCVCPUDef
can also be const.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5f687d77ff93ae3dd2fb48600e4e6ae32eb7350e
https://github.com/qemu/qemu/commit/5f687d77ff93ae3dd2fb48600e4e6ae32eb7350e
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert THead C906 to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 09ef7d97454a64e00d8dc9fd3a188d6c06003cc1
https://github.com/qemu/qemu/commit/09ef7d97454a64e00d8dc9fd3a188d6c06003cc1
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert TT Ascalon to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0927f7d55cd5a214eb2ef9671ddd271a3fb2a15c
https://github.com/qemu/qemu/commit/0927f7d55cd5a214eb2ef9671ddd271a3fb2a15c
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert Ventana V1 to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 70f48d7fb19a88bca3cd4c388646d4cb9ee730f0
https://github.com/qemu/qemu/commit/70f48d7fb19a88bca3cd4c388646d4cb9ee730f0
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 42bc8af14033b9eeeb535449f243767c015f027e
https://github.com/qemu/qemu/commit/42bc8af14033b9eeeb535449f243767c015f027e
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove .instance_post_init
Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.
In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end of riscv_cpu_init().
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 220c739903cec99df032219ac94c45b5269a0ab5
https://github.com/qemu/qemu/commit/220c739903cec99df032219ac94c45b5269a0ab5
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M include/qom/object.h
M qom/object.c
Log Message:
-----------
qom: reverse order of instance_post_init calls
Currently, the instance_post_init calls are performed from the leaf
class and all the way up to Object. This is incorrect because the
leaf class cannot observe property values applied by the superclasses;
for example, a compat property will be set on a device *after*
the class's post_init callback has run.
In particular this makes it impossible for implementations of
accel_cpu_instance_init() to operate based on the actual values of
the properties, though it seems that cxl_dsp_instance_post_init and
rp_instance_post_init might have similar issues.
Follow instead the same order as instance_init, starting with Object
and running the child class's instance_post_init after the parent.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f0737158b483e7ec2b2512145aeab888b85cc1f7
https://github.com/qemu/qemu/commit/f0737158b483e7ec2b2512145aeab888b85cc1f7
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M hw/i386/sgx-stub.c
M hw/i386/sgx.c
M hw/pci-host/gt64120.c
M hw/pci/pci_host.c
M hw/riscv/boot.c
M hw/riscv/virt-acpi-build.c
M hw/riscv/virt.c
M include/hw/pci-host/dino.h
M include/hw/pci/pci_host.h
M include/qom/object.h
M qapi/misc-target.json
M qom/object.c
M target/i386/cpu.c
M target/i386/hvf/x86_cpuid.c
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
A target/riscv/cpu_cfg_fields.h.inc
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/th_csr.c
M target/riscv/translate.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/riscv: clean up supported MMU modes, declarative CPU definitions,
remove .instance_post_init (reviewed by Alistair)
* qom: reverse order of instance_post_init calls
* qapi/misc-target: doc and standard improvements for SGX
* hw/pci-host/gt64120: Fix endianness handling
* i386/hvf: Make CPUID_HT supported
* i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 20 May 2025 03:16:27 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [full]
# gpg: aka "Paolo Bonzini <[email protected]>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits)
qom: reverse order of instance_post_init calls
target/riscv: remove .instance_post_init
target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
target/riscv: convert Ventana V1 to RISCVCPUDef
target/riscv: convert TT Ascalon to RISCVCPUDef
target/riscv: convert THead C906 to RISCVCPUDef
target/riscv: generalize custom CSR functionality
target/riscv: th: make CSR insertion test a bit more intuitive
target/riscv: convert SiFive U models to RISCVCPUDef
target/riscv: convert ibex CPU models to RISCVCPUDef
target/riscv: convert SiFive E CPU models to RISCVCPUDef
target/riscv: convert dynamic CPU models to RISCVCPUDef
target/riscv: convert bare CPU models to RISCVCPUDef
target/riscv: convert profile CPU models to RISCVCPUDef
target/riscv: convert abstract CPU classes to RISCVCPUDef
target/riscv: add more RISCVCPUDef fields
target/riscv: include default value in cpu_cfg_fields.h.inc
target/riscv: move RISCVCPUConfig fields to a header file
target/riscv: merge riscv_cpu_class_init with the class_base function
target/riscv: store RISCVCPUDef struct directly in the class
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/2af4a82ab2cc...f0737158b483
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