Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 4ec799dd17dcbb0fa4e90e685d5d6fcf8f72338a
https://github.com/qemu/qemu/commit/4ec799dd17dcbb0fa4e90e685d5d6fcf8f72338a
Author: Clément Chigot <[email protected]>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M target/sparc/fop_helper.c
Log Message:
-----------
target/sparc: don't set FSR_NVA when comparing unordered floats
FSR_NVA should be set when one of the operands is a signaling NaN or
when using FCMPEx instructions. But those cases are already handled
within check_ieee_exception or floatxx_compare functions.
Otherwise, it should be left untouched.
FTR, this was detected by inf-compare-[5678] tests within gcc
testsuites.
Signed-off-by: Clément Chigot <[email protected]>
Message-Id: <[email protected]>
Acked-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>
Commit: 428d1789df911bc863e55eed2d8f33ce991cbd09
https://github.com/qemu/qemu/commit/428d1789df911bc863e55eed2d8f33ce991cbd09
Author: Markus Armbruster <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
Log Message:
-----------
docs/about: Belatedly document tightening of QMP device_add checking
Commit 4d8b0f0a9536 (v6.2.0) deprecated incorrectly typed device_add
arguments. Commit be93fd53723c (qdev-monitor: avoid QemuOpts in QMP
device_add) fixed them for v9.2.0, but neglected to update
documentation. Do that now.
Cc: Stefan Hajnoczi <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Stefan Hajnoczi <[email protected]>
[Commit message typo corrected]
Commit: c2fb6eaeb9d479a80b104914f459a0c6c32e5a88
https://github.com/qemu/qemu/commit/c2fb6eaeb9d479a80b104914f459a0c6c32e5a88
Author: Markus Armbruster <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M qapi/migration.json
Log Message:
-----------
qapi/migration: Deprecate migrate argument @detach
Argument @detach has always been ignored. Start the clock to get rid
of it.
Cc: Peter Xu <[email protected]>
Cc: Fabiano Rosas <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Message-ID: <[email protected]>
ACKed-by: Peter Krempa <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Commit: 977dfcd552d0bef725f89bcabcedeb51593000ab
https://github.com/qemu/qemu/commit/977dfcd552d0bef725f89bcabcedeb51593000ab
Author: Markus Armbruster <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs/about/deprecated: Move deprecation notes to tidy up order
The deprecation notes within a section are mostly in version order.
Move the few that aren't so they are.
Signed-off-by: Markus Armbruster <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Commit: 662b85aae131e7cb8dd8b03c9e44a95bc87573ca
https://github.com/qemu/qemu/commit/662b85aae131e7cb8dd8b03c9e44a95bc87573ca
Author: Markus Armbruster <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/removed-features.rst
Log Message:
-----------
docs/about/removed-features: Move removal notes to tidy up order
The removal notes within a section are mostly in version order. Move
the few that aren't so they are.
Signed-off-by: Markus Armbruster <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Commit: 319b0c8d077401f51bf6314039b82db20d5267ee
https://github.com/qemu/qemu/commit/319b0c8d077401f51bf6314039b82db20d5267ee
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW
When we moved TLB_MMIO and TLB_DISCARD_WRITE to TLB_SLOW_FLAGS_MASK,
we failed to update atomic_mmu_lookup to properly reconstruct flags.
Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow
flags")
Reported-by: Jonathan Cameron <[email protected]>
Tested-by: Jonathan Cameron <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 556d05d1e2ac687463ce2877cb4acd1b0589deed
https://github.com/qemu/qemu/commit/556d05d1e2ac687463ce2877cb4acd1b0589deed
Author: Pierrick Bouvier <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M system/main.c
Log Message:
-----------
system/main: comment lock rationale
Signed-off-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 19f036726a416c9248c19befe544a2d30b099a25
https://github.com/qemu/qemu/commit/19f036726a416c9248c19befe544a2d30b099a25
Author: Andreas Schwab <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: implement pgid field of /proc/self/stat
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 67f2d507ca444cfff993c1a05df3aaa4346a372c
https://github.com/qemu/qemu/commit/67f2d507ca444cfff993c1a05df3aaa4346a372c
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.c
Log Message:
-----------
target/microblaze: Split out mb_unaligned_access_internal
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3f8d6b432dbdd63eecfb454d59d36b08f76c0c95
https://github.com/qemu/qemu/commit/3f8d6b432dbdd63eecfb454d59d36b08f76c0c95
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.c
M target/microblaze/helper.h
Log Message:
-----------
target/microblaze: Introduce helper_unaligned_access
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 526b0d364af081792e469adabbc67aeaca8a4343
https://github.com/qemu/qemu/commit/526b0d364af081792e469adabbc67aeaca8a4343
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/op_helper.c
Log Message:
-----------
target/microblaze: Split out mb_transaction_failed_internal
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: beea772666fb1bb86136042fd8ee7140a01bb36f
https://github.com/qemu/qemu/commit/beea772666fb1bb86136042fd8ee7140a01bb36f
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.h
M target/microblaze/op_helper.c
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Implement extended address load/store out of line
Use helpers and address_space_ld/st instead of inline
loads and stores. This allows us to perform operations
on physical addresses wider than virtual addresses.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8cea8bd4d3909b7828310a0f76d5194d1bf0095a
https://github.com/qemu/qemu/commit/8cea8bd4d3909b7828310a0f76d5194d1bf0095a
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/cpu.h
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Use uint64_t for CPUMBState.ear
Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 14c1d81354c425d98423c41f60db5907f70cf216
https://github.com/qemu/qemu/commit/14c1d81354c425d98423c41f60db5907f70cf216
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
Use an explicit 64-bit type for extended addresses.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 17ac97a9581fa9dd9c433d7562506a514f7292b3
https://github.com/qemu/qemu/commit/17ac97a9581fa9dd9c433d7562506a514f7292b3
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/mmu.c
Log Message:
-----------
target/microblaze: Fix printf format in mmu_translate
Use TARGET_FMT_lx to match the target_ulong type of vaddr.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b52ee0c1a4205c8d698c37557401d2f55e071fba
https://github.com/qemu/qemu/commit/b52ee0c1a4205c8d698c37557401d2f55e071fba
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M configs/targets/microblaze-softmmu.mak
M configs/targets/microblazeel-softmmu.mak
Log Message:
-----------
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bd07403fc146a9bfc5312404a63f24cc48701c97
https://github.com/qemu/qemu/commit/bd07403fc146a9bfc5312404a63f24cc48701c97
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Drop DisasContext.r0
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 36a9529e60e09b0d0b6b5ebad614255c97bf9322
https://github.com/qemu/qemu/commit/36a9529e60e09b0d0b6b5ebad614255c97bf9322
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Simplify compute_ldst_addr_type{a,b}
Require TCGv_i32 and TCGv be identical, so drop
the extensions. Return constants when possible
instead of a mov into a temporary. Return register
inputs unchanged when possible.
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9cfcf8c3b7b7a95e754a9fce565a88c6c76ce128
https://github.com/qemu/qemu/commit/9cfcf8c3b7b7a95e754a9fce565a88c6c76ce128
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg: Drop TCGContext.tlb_dyn_max_bits
This was an extremely minor optimization for aarch64
and x86_64, to use a 32-bit AND instruction when the
guest softmmu tlb maximum was sufficiently small.
Both hosts can simply use a 64-bit AND insn instead.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 11efde54f248c2da9e164910b8b1945e78a7168e
https://github.com/qemu/qemu/commit/11efde54f248c2da9e164910b8b1945e78a7168e
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/perf.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
tcg: Drop TCGContext.page_{mask,bits}
Use exec/target_page.h instead of independent variables.
Signed-off-by: Richard Henderson <[email protected]>
Commit: eb978e50e42f3439e7a7a104e76aafc81bc4a028
https://github.com/qemu/qemu/commit/eb978e50e42f3439e7a7a104e76aafc81bc4a028
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Use MO_ALIGN for system UNALIGN()
This should have been done before removing TARGET_ALIGNED_ONLY,
as we did for hppa and alpha.
Cc: Yoshinori Sato <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Fixes: 8244189419f9 ("target/sh4: Remove TARGET_ALIGNED_ONLY")
Signed-off-by: Richard Henderson <[email protected]>
Commit: bdf26b5d16dd2264553308aa6bbf24b4749fcc07
https://github.com/qemu/qemu/commit/bdf26b5d16dd2264553308aa6bbf24b4749fcc07
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
Log Message:
-----------
accel/tcg: Add TCGCPUOps.pointer_wrap
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a4027ed7d4becb4cb67c912c75ecd4846b148829
https://github.com/qemu/qemu/commit/a4027ed7d4becb4cb67c912c75ecd4846b148829
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
M target/alpha/cpu.c
M target/hppa/cpu.c
M target/sh4/cpu.c
Log Message:
-----------
target: Use cpu_pointer_wrap_notreached for strict align targets
Alpha, HPPA, and SH4 always use aligned addresses,
and therefore never produce accesses that cross pages.
Cc: Helge Deller <[email protected]>
Cc: Yoshinori Sato <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 981f2beb161b9bcaeedc1f91ad22bff255856cb2
https://github.com/qemu/qemu/commit/981f2beb161b9bcaeedc1f91ad22bff255856cb2
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
M target/avr/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/openrisc/cpu.c
M target/rx/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets. AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.
Cc: Michael Rolnik <[email protected]>
Cc: Laurent Vivier <[email protected]>
Cc: Stafford Horne <[email protected]>
Cc: Yoshinori Sato <[email protected]>
Cc: Max Filippov <[email protected]>
Tested-by Bastian Koppelmann <[email protected]> (tricore)
Reviewed-by: Bastian Koppelmann <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d21144a48c1a9d1998c594d976d5e906276eca4c
https://github.com/qemu/qemu/commit/d21144a48c1a9d1998c594d976d5e906276eca4c
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
Log Message:
-----------
target/arm: Fill in TCGCPUOps.pointer_wrap
For a-profile, check A32 vs A64 state.
For m-profile, use cpu_pointer_wrap_uint32.
Cc: [email protected]
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7174cd2eec67d9b7bf969cdc87e656b4c4c93465
https://github.com/qemu/qemu/commit/7174cd2eec67d9b7bf969cdc87e656b4c4c93465
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/tcg/tcg-cpu.c
Log Message:
-----------
target/i386: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit state.
Cc: Paolo Bonzini <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 353f703cf1959228affc23b5bba8a18738736cf4
https://github.com/qemu/qemu/commit/353f703cf1959228affc23b5bba8a18738736cf4
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Fill in TCGCPUOps.pointer_wrap
Check va32 state.
Reviewed-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 396c12d00e3944e79159c9f3cb934f26f32ef861
https://github.com/qemu/qemu/commit/396c12d00e3944e79159c9f3cb934f26f32ef861
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit addressing state.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4031eb4facfd8793defeb83c05712643c161e32e
https://github.com/qemu/qemu/commit/4031eb4facfd8793defeb83c05712643c161e32e
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit state.
Cc: [email protected]
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8024f004155ea5a3f492c35a792ea7863176e1a9
https://github.com/qemu/qemu/commit/8024f004155ea5a3f492c35a792ea7863176e1a9
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit and pointer masking state.
Cc: [email protected]
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c2a0439f1ee99cb29883311f75ba08d9cca759c9
https://github.com/qemu/qemu/commit/c2a0439f1ee99cb29883311f75ba08d9cca759c9
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/s390x/cpu.c
Log Message:
-----------
target/s390x: Fill in TCGCPUOps.pointer_wrap
Use the existing wrap_address function.
Cc: [email protected]
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 90f80e4b0fedfc78163c1c112bb74ccbfcae2365
https://github.com/qemu/qemu/commit/90f80e4b0fedfc78163c1c112bb74ccbfcae2365
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Fill in TCGCPUOps.pointer_wrap
Check address masking state for sparc64.
Cc: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5c2891601ccdaa41427187ef95bc25c828b355e4
https://github.com/qemu/qemu/commit/5c2891601ccdaa41427187ef95bc25c828b355e4
Author: Richard Henderson <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Assert TCGCPUOps.pointer_wrap is set
All targets now provide the function, so we can
make the call unconditional.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f88934b61ee0dc1d583f0a576ce87ed2ff9c116b
https://github.com/qemu/qemu/commit/f88934b61ee0dc1d583f0a576ce87ed2ff9c116b
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sparc/fop_helper.c
Log Message:
-----------
Merge tag 'qemu-sparc-20250527' of https://github.com/mcayland/qemu into
staging
qemu-sparc queue
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 27 May 2025 17:16:20 EDT
# gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Mark Cave-Ayland <[email protected]>"
[full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* tag 'qemu-sparc-20250527' of https://github.com/mcayland/qemu:
target/sparc: don't set FSR_NVA when comparing unordered floats
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 3072961b6edc99abfbd87caac3de29bb58a52ccf
https://github.com/qemu/qemu/commit/3072961b6edc99abfbd87caac3de29bb58a52ccf
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/translate-all.c
M configs/targets/microblaze-softmmu.mak
M configs/targets/microblazeel-softmmu.mak
M include/accel/tcg/cpu-ops.h
M include/tcg/tcg.h
M linux-user/syscall.c
M system/main.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/helper.c
M target/microblaze/helper.h
M target/microblaze/mmu.c
M target/microblaze/op_helper.c
M target/microblaze/translate.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/perf.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW
linux-user: implement pgid field of /proc/self/stat
target/sh4: Use MO_ALIGN for system UNALIGN()
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
accel/tcg: Add TCGCPUOps.pointer_wrap
target/*: Populate TCGCPUOps.pointer_wrap
# -----BEGIN PGP SIGNATURE-----
#
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# RFzK4A==
# =XQzq
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 28 May 2025 04:13:04 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu: (28 commits)
accel/tcg: Assert TCGCPUOps.pointer_wrap is set
target/sparc: Fill in TCGCPUOps.pointer_wrap
target/s390x: Fill in TCGCPUOps.pointer_wrap
target/riscv: Fill in TCGCPUOps.pointer_wrap
target/ppc: Fill in TCGCPUOps.pointer_wrap
target/mips: Fill in TCGCPUOps.pointer_wrap
target/loongarch: Fill in TCGCPUOps.pointer_wrap
target/i386: Fill in TCGCPUOps.pointer_wrap
target/arm: Fill in TCGCPUOps.pointer_wrap
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
target: Use cpu_pointer_wrap_notreached for strict align targets
accel/tcg: Add TCGCPUOps.pointer_wrap
target/sh4: Use MO_ALIGN for system UNALIGN()
tcg: Drop TCGContext.page_{mask,bits}
tcg: Drop TCGContext.tlb_dyn_max_bits
target/microblaze: Simplify compute_ldst_addr_type{a,b}
target/microblaze: Drop DisasContext.r0
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
target/microblaze: Fix printf format in mmu_translate
target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: a5519f27a243d11191d462ef4f5b5d71aeef2271
https://github.com/qemu/qemu/commit/a5519f27a243d11191d462ef4f5b5d71aeef2271
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M qapi/migration.json
Log Message:
-----------
Merge tag 'pull-misc-2025-05-28' of https://repo.or.cz/qemu/armbru into
staging
Miscellaneous patches for 2025-05-28
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 28 May 2025 08:03:30 EDT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "[email protected]"
# gpg: Good signature from "Markus Armbruster <[email protected]>" [full]
# gpg: aka "Markus Armbruster <[email protected]>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-misc-2025-05-28' of https://repo.or.cz/qemu/armbru:
docs/about/removed-features: Move removal notes to tidy up order
docs/about/deprecated: Move deprecation notes to tidy up order
qapi/migration: Deprecate migrate argument @detach
docs/about: Belatedly document tightening of QMP device_add checking
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/80db93b2b88f...a5519f27a243
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