[Qemu-commits] [qemu/qemu] 9526b9: hw/arm/highbank: Mark the "highbank" and the "midw...

[stefanhaRH via Qemu-commits]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9526b9b620c78a1336bca1b55a562fad23208392
      
https://github.com/qemu/qemu/commit/9526b9b620c78a1336bca1b55a562fad23208392
  Author: Thomas Huth <th...@redhat.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M docs/about/deprecated.rst
    M hw/arm/highbank.c

  Log Message:
  -----------
  hw/arm/highbank: Mark the "highbank" and the "midway" machine as deprecated

We don't have any automatic regression tests for these machines and
when asking the usual suspects on the mailing list we came to the
conclusion that nobody tests these machines manually, too, so it seems
like this is currently just completely unused code. Mark them as depre-
cated to see whether anybody still speaks up during the deprecation
period, otherwise we can likely remove these two machines in a couple
of releases.

Signed-off-by: Thomas Huth <th...@redhat.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 20250702113051.46483-1-th...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
[PMM: tweaked deprecation.rst text]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 597ae563ba2a46174a414a3d223db4aac9a76cd3
      
https://github.com/qemu/qemu/commit/597ae563ba2a46174a414a3d223db4aac9a76cd3
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/stubs/kvm-stub.c

  Log Message:
  -----------
  accel/kvm: Remove kvm_init_cpu_signals() stub

Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_init_cpu_signals() stub is not necessary.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-6-phi...@linaro.org>


  Commit: af065855ced71fdad6fc0fecec7dd65593b73413
      
https://github.com/qemu/qemu/commit/af065855ced71fdad6fc0fecec7dd65593b73413
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/kvm/kvm-all.c
    M include/system/kvm.h

  Log Message:
  -----------
  accel/kvm: Reduce kvm_create_vcpu() declaration scope

kvm_create_vcpu() is only used within the same file unit.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-7-phi...@linaro.org>


  Commit: 7359f690095bea8466bef2b7b822bb4d2962dbb4
      
https://github.com/qemu/qemu/commit/7359f690095bea8466bef2b7b822bb4d2962dbb4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/monitor.c
    M hmp-commands-info.hx
    M qapi/machine.json
    M tests/qtest/qmp-cmd-test.c

  Log Message:
  -----------
  accel/tcg: Remove 'info opcount' and @x-query-opcount

Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:

  (qemu) info opcount
  [TCG profiler not compiled]

Remove that unstable and unuseful command.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Dr. David Alan Gilbert <d...@treblig.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-8-phi...@linaro.org>


  Commit: 93d7064e594f442235d7d9442005f4404a7a5004
      
https://github.com/qemu/qemu/commit/93d7064e594f442235d7d9442005f4404a7a5004
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/monitor.c

  Log Message:
  -----------
  accel/tcg: Remove profiler leftover

TCG profiler was removed in commit 1b65b4f54c7.

Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-9-phi...@linaro.org>


  Commit: 8becf103741bd1b50b827bc3cd60872e9f36e981
      
https://github.com/qemu/qemu/commit/8becf103741bd1b50b827bc3cd60872e9f36e981
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/monitor.c

  Log Message:
  -----------
  accel/tcg: Factor tcg_dump_flush_info() out

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-10-phi...@linaro.org>


  Commit: 3955a104bca098b820a0b57bb411281ae5cac498
      
https://github.com/qemu/qemu/commit/3955a104bca098b820a0b57bb411281ae5cac498
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/internal-common.h
    M accel/tcg/monitor.c

  Log Message:
  -----------
  accel/tcg: Factor tcg_dump_stats() out for re-use

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-11-phi...@linaro.org>


  Commit: 6bb8f2c51b28ce35c83ac4e53bbd85ef37d787c4
      
https://github.com/qemu/qemu/commit/6bb8f2c51b28ce35c83ac4e53bbd85ef37d787c4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/tcg-accel-ops-mttcg.c
    M accel/tcg/tcg-accel-ops.c

  Log Message:
  -----------
  accel/tcg: Clear exit_request once in tcg_cpu_exec()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250701144017.43487-62-phi...@linaro.org>


  Commit: dd0b228552e4b1d3b680ff4e8033a110536fdc4c
      
https://github.com/qemu/qemu/commit/dd0b228552e4b1d3b680ff4e8033a110536fdc4c
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/tcg-accel-ops-rr.c

  Log Message:
  -----------
  accel/tcg: Unregister the RCU before exiting RR thread

Although unreachable, still unregister the RCU before exiting
the thread, as documented in "qemu/rcu.h":

 /*
  * Important !
  *
  * Each thread containing read-side critical sections must be registered
  * with rcu_register_thread() before calling rcu_read_lock().
  * rcu_unregister_thread() should be called before the thread exits.
  */

Unregister the RCU to be on par with what is done for other
accelerators.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250702185332.43650-66-phi...@linaro.org>


  Commit: 4dc480e7da9c389c069da250a6e9252ee9fa0659
      
https://github.com/qemu/qemu/commit/4dc480e7da9c389c069da250a6e9252ee9fa0659
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M include/system/hvf.h
    M include/system/hvf_int.h

  Log Message:
  -----------
  accel/hvf: Restrict internal declarations

Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-15-phi...@linaro.org>


  Commit: 3240b69f683865f0c098669608add5414e532da1
      
https://github.com/qemu/qemu/commit/3240b69f683865f0c098669608add5414e532da1
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/hvf/hvf-all.c

  Log Message:
  -----------
  accel/hvf: Move per-cpu method declarations to hvf-accel-ops.c

hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-16-phi...@linaro.org>


  Commit: 81490432b667ada39d51247aa56f51110bcb595a
      
https://github.com/qemu/qemu/commit/81490432b667ada39d51247aa56f51110bcb595a
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/hvf/hvf-all.c

  Log Message:
  -----------
  accel/hvf: Move generic method declarations to hvf-all.c

hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-17-phi...@linaro.org>


  Commit: 5f3bfbd8e2453671176e9759b9dc14584cd11e79
      
https://github.com/qemu/qemu/commit/5f3bfbd8e2453671176e9759b9dc14584cd11e79
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-all.c

  Log Message:
  -----------
  accel/hvf: Report missing com.apple.security.hypervisor entitlement

We need the QEMU binary signed to be able to use HVF.
Improve the following:

  $ ./qemu-system-aarch64-unsigned -M virt -accel hvf
  qemu-system-aarch64-unsigned: -accel hvf: Error: ret = HV_DENIED (0xfae94007, 
at ../../accel/hvf/hvf-accel-ops.c:339)
  Abort trap: 6

to:

  $ ./qemu-system-aarch64-unsigned -M virt -accel hvf
  qemu-system-aarch64-unsigned: -accel hvf: Could not access HVF. Is the 
executable signed with com.apple.security.hypervisor entitlement?

Suggested-by: Shatyuka <shaty...@qq.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2800
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Mads Ynddal <m...@ynddal.dk>
Message-Id: <20250702185332.43650-29-phi...@linaro.org>


  Commit: b6340f5866e19deadae8c19399907fed938d8d1f
      
https://github.com/qemu/qemu/commit/b6340f5866e19deadae8c19399907fed938d8d1f
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M include/hw/core/cpu.h

  Log Message:
  -----------
  cpus: Document CPUState::vcpu_dirty field

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-Id: <20250703173248.44995-18-phi...@linaro.org>


  Commit: 6f13a0ada0160d420f1e4945ee53a1abdae33a1c
      
https://github.com/qemu/qemu/commit/6f13a0ada0160d420f1e4945ee53a1abdae33a1c
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M include/system/hvf_int.h
    M target/arm/hvf/hvf.c
    M target/i386/hvf/hvf.c
    M target/i386/hvf/x86hvf.c

  Log Message:
  -----------
  accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field

No need for accel-specific @dirty field when we have
a generic one in CPUState.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Mads Ynddal <m...@ynddal.dk>
Message-Id: <20250703173248.44995-19-phi...@linaro.org>


  Commit: ffd8ee9d7cbd220d15526d14d5b3402a63eab0ff
      
https://github.com/qemu/qemu/commit/ffd8ee9d7cbd220d15526d14d5b3402a63eab0ff
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/i386/nvmm/nvmm-all.c

  Log Message:
  -----------
  accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field

No need for accel-specific @dirty field when we have
a generic one in CPUState.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-20-phi...@linaro.org>


  Commit: 36ab216b81deaca2a6a39be803e870dead2b13f0
      
https://github.com/qemu/qemu/commit/36ab216b81deaca2a6a39be803e870dead2b13f0
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field

No need for accel-specific @dirty field when we have
a generic one in CPUState.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-21-phi...@linaro.org>


  Commit: 888a6be77560992d17ab823f27a8297ecd7893b6
      
https://github.com/qemu/qemu/commit/888a6be77560992d17ab823f27a8297ecd7893b6
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/stubs/kvm-stub.c

  Log Message:
  -----------
  accel/kvm: Remove kvm_cpu_synchronize_state() stub

Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.

Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-22-phi...@linaro.org>


  Commit: 8e825755c5ddcdfd91e585d850aecee434d2ff63
      
https://github.com/qemu/qemu/commit/8e825755c5ddcdfd91e585d850aecee434d2ff63
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M include/system/accel-ops.h
    M include/system/hw_accel.h

  Log Message:
  -----------
  accel/system: Document cpu_synchronize_state()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-23-phi...@linaro.org>


  Commit: 04bd6c3631e0184dcafb0403e0248a2052585914
      
https://github.com/qemu/qemu/commit/04bd6c3631e0184dcafb0403e0248a2052585914
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M include/system/accel-ops.h
    M include/system/hw_accel.h

  Log Message:
  -----------
  accel/system: Document cpu_synchronize_state_post_init/reset()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-24-phi...@linaro.org>


  Commit: 80a1efdedd3099cde51cabf91789e037a6af11df
      
https://github.com/qemu/qemu/commit/80a1efdedd3099cde51cabf91789e037a6af11df
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M MAINTAINERS
    M accel/stubs/meson.build
    A accel/stubs/nvmm-stub.c
    M include/system/nvmm.h
    M target/i386/nvmm/nvmm-all.c

  Log Message:
  -----------
  accel/nvmm: Expose nvmm_enabled() to common code

Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-25-phi...@linaro.org>


  Commit: a9c2afd74b887b4775f425b72be1888220594bb5
      
https://github.com/qemu/qemu/commit/a9c2afd74b887b4775f425b72be1888220594bb5
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M MAINTAINERS
    M accel/stubs/meson.build
    A accel/stubs/whpx-stub.c
    M include/system/whpx.h
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  accel/whpx: Expose whpx_enabled() to common code

Currently whpx_enabled() is restricted to target-specific code.
By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-26-phi...@linaro.org>


  Commit: 20a0181600d61f5e58a087be14bd63c40aca2cd4
      
https://github.com/qemu/qemu/commit/20a0181600d61f5e58a087be14bd63c40aca2cd4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M MAINTAINERS
    M accel/dummy-cpus.c
    A accel/dummy-cpus.h
    M accel/qtest/qtest.c
    M accel/xen/xen-all.c
    M include/system/cpus.h

  Log Message:
  -----------
  accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'

'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-27-phi...@linaro.org>


  Commit: b64bb17d14a62ea04b605f81daec8a5a4fad3be4
      
https://github.com/qemu/qemu/commit/b64bb17d14a62ea04b605f81daec8a5a4fad3be4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/kvm/kvm-accel-ops.c
    M accel/qtest/qtest.c
    M accel/xen/xen-all.c
    M include/system/accel-ops.h
    M system/cpus.c
    M target/i386/nvmm/nvmm-accel-ops.c
    M target/i386/whpx/whpx-accel-ops.c

  Log Message:
  -----------
  accel: Expose and register generic_handle_interrupt()

In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.

Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Mads Ynddal <m...@ynddal.dk>
Message-Id: <20250703173248.44995-29-phi...@linaro.org>


  Commit: 487b25c9d93add2e0e58275d7c1ef89810fad763
      
https://github.com/qemu/qemu/commit/487b25c9d93add2e0e58275d7c1ef89810fad763
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/accel-system.c
    M accel/tcg/tcg-accel-ops.c
    M include/qemu/accel.h
    M include/system/accel-ops.h

  Log Message:
  -----------
  accel: Keep reference to AccelOpsClass in AccelClass

Allow dereferencing AccelOpsClass outside of accel/accel-system.c.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-30-phi...@linaro.org>


  Commit: fa8f6f25ea8dc3a1123deaf53cf4907005880e52
      
https://github.com/qemu/qemu/commit/fa8f6f25ea8dc3a1123deaf53cf4907005880e52
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/m_helper.c

  Log Message:
  -----------
  target/arm: Bring VLSTM/VLLDM helper store/load closer to the ARM pseudocode

This patch brings the VLSTM and VLLDM helper functions closer to the ARM
pseudocode by adding MO_ALIGN to the MemOpIdx of the associated store
(`cpu_stl_mmu`) operations and load (`cpu_ldl_mmu`) operations.

Note that this is not a bug fix: an 8-byte alignment check already exists
and remains in place, enforcing stricter alignment than the 4 bytes
requirement in the individual loads and stores. This change merely makes the
helper implementations closer to the ARM pseudocode.

That said, as a side effect, the MMU index is now resolved once instead of
on every `cpu_*_data_ra` call, reducing redundant lookups

Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-2-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 94b07a46d1dbf1c31373da14e14f88b65ff94181
      
https://github.com/qemu/qemu/commit/94b07a46d1dbf1c31373da14e14f88b65ff94181
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/m_helper.c

  Log Message:
  -----------
  target/arm: Fix BLXNS helper store alignment checks

This patch adds alignment checks in the store operations (when stacking the
return pc and psr) in the BLXNS instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-3-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c4940752ae12b82938c95a9cfe0864b725ac85f1
      
https://github.com/qemu/qemu/commit/c4940752ae12b82938c95a9cfe0864b725ac85f1
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/m_helper.c

  Log Message:
  -----------
  target/arm: Fix function_return helper load alignment checks

This patch adds alignment checks in the load operations (when unstacking the
return pc and psr) in the FunctionReturn pseudocode.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-4-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 56249f3e6ceb4076b9d1b2500450420cf18346e2
      
https://github.com/qemu/qemu/commit/56249f3e6ceb4076b9d1b2500450420cf18346e2
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VLDR helper load alignment checks

This patch adds alignment checks in the load operations in the VLDR
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-5-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c8bde49179be1196d8ccfcfdc6269ce3861053a5
      
https://github.com/qemu/qemu/commit/c8bde49179be1196d8ccfcfdc6269ce3861053a5
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VSTR helper store alignment checks

This patch adds alignment checks in the store operations in the VSTR
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-6-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f8436889a0c8468b5cb7b881a5d62283a27c44b6
      
https://github.com/qemu/qemu/commit/f8436889a0c8468b5cb7b881a5d62283a27c44b6
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VLDR_SG helper load alignment checks

This patch adds alignment checks in the load operations in the VLDR_SG
instructions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-7-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 13ab3764ea0c0e43e2258e1755c08551c8eb8e60
      
https://github.com/qemu/qemu/commit/13ab3764ea0c0e43e2258e1755c08551c8eb8e60
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VSTR_SG helper store alignment checks

This patch adds alignment checks in the store operations in the VSTR_SG
instructions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-8-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a7498d625fb18d44a42b87af6051295259142437
      
https://github.com/qemu/qemu/commit/a7498d625fb18d44a42b87af6051295259142437
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VLD4 helper load alignment checks

This patch adds alignment checks in the load operations in the VLD4
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-9-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 26aa0e36bfdbbc0f4b07b4ea51e910c4dc43e890
      
https://github.com/qemu/qemu/commit/26aa0e36bfdbbc0f4b07b4ea51e910c4dc43e890
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VLD2 helper load alignment checks

This patch adds alignment checks in the load operations in the VLD2
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-10-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 28b3745991add8c3488c0c984bf17a235d70329b
      
https://github.com/qemu/qemu/commit/28b3745991add8c3488c0c984bf17a235d70329b
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VST4 helper store alignment checks

This patch adds alignment checks in the store operations in the VST4
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-11-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c9bc9f57ffbafea6bb9fe45610b9a1e9ff33e990
      
https://github.com/qemu/qemu/commit/c9bc9f57ffbafea6bb9fe45610b9a1e9ff33e990
  Author: William Kosasih <kosasihwilli...@gmail.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VST2 helper store alignment checks

This patch adds alignment checks in the store operations in the VST2
instruction.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih <kosasihwilli...@gmail.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250703085604.154449-12-kosasihwilli...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9d01d2e86d450f12f275bd64aeb022e8423e220c
      
https://github.com/qemu/qemu/commit/9d01d2e86d450f12f275bd64aeb022e8423e220c
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/accel-system.c
    M accel/hvf/hvf-all.c
    M accel/kvm/kvm-all.c
    M accel/qtest/qtest.c
    M accel/tcg/tcg-all.c
    M accel/xen/xen-all.c
    M bsd-user/main.c
    M include/qemu/accel.h
    M linux-user/main.c
    M target/i386/nvmm/nvmm-all.c
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  accel: Propagate AccelState to AccelClass::init_machine()

In order to avoid init_machine() to call current_accel(),
pass AccelState along.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-31-phi...@linaro.org>


  Commit: d8878e4fcaf3dfe591b18a06760831c041402d15
      
https://github.com/qemu/qemu/commit/d8878e4fcaf3dfe591b18a06760831c041402d15
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/hvf/hvf-all.c

  Log Message:
  -----------
  accel/hvf: Re-use QOM allocated state

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250606164418.98655-8-phi...@linaro.org>


  Commit: 7bdeb984cd3a382ec2b22b8b8c4a5207c316482f
      
https://github.com/qemu/qemu/commit/7bdeb984cd3a382ec2b22b8b8c4a5207c316482f
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/tcg/tcg-all.c

  Log Message:
  -----------
  accel/tcg: Prefer local AccelState over global current_accel()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-33-phi...@linaro.org>


  Commit: 4bc5c9ab62f28f66f83648c82508cce16d805a0d
      
https://github.com/qemu/qemu/commit/4bc5c9ab62f28f66f83648c82508cce16d805a0d
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/kvm/kvm-all.c

  Log Message:
  -----------
  accel/kvm: Prefer local AccelState over global MachineState::accel

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-32-phi...@linaro.org>


  Commit: 6b1ce32fee6879d1d09070dfde0d14cbbeaced5c
      
https://github.com/qemu/qemu/commit/6b1ce32fee6879d1d09070dfde0d14cbbeaced5c
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/kvm/kvm-all.c

  Log Message:
  -----------
  accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-35-phi...@linaro.org>


  Commit: 14784d00ce6643077d3b9f24c19cb2882c173ff2
      
https://github.com/qemu/qemu/commit/14784d00ce6643077d3b9f24c19cb2882c173ff2
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/kvm/kvm-all.c
    M include/qemu/accel.h
    M system/memory.c

  Log Message:
  -----------
  accel: Directly pass AccelState argument to AccelClass::has_memory()

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-34-phi...@linaro.org>


  Commit: c7212fd2ce9182ec205dd22ff5bc66864fb3cd10
      
https://github.com/qemu/qemu/commit/c7212fd2ce9182ec205dd22ff5bc66864fb3cd10
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/accel-system.c
    M accel/xen/xen-all.c
    M include/qemu/accel.h

  Log Message:
  -----------
  accel: Remove unused MachineState argument of AccelClass::setup_post()

This method only accesses xen_domid/xen_domid_restrict, which are both
related to the 'accelerator', not the machine. Besides, xen_domid aims
to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict
QOM property.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-36-phi...@linaro.org>


  Commit: 261573c7724ffca8795416eae8b435e175672491
      
https://github.com/qemu/qemu/commit/261573c7724ffca8795416eae8b435e175672491
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/accel-common.c
    M accel/hvf/hvf-all.c
    M accel/kvm/kvm-all.c
    M accel/tcg/tcg-all.c
    M include/qemu/accel.h

  Log Message:
  -----------
  accel: Pass AccelState argument to gdbstub_supported_sstep_flags()

In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-37-phi...@linaro.org>


  Commit: 9a8e6b9ca1a6cf5aa66f0f7f9620a0b90320b064
      
https://github.com/qemu/qemu/commit/9a8e6b9ca1a6cf5aa66f0f7f9620a0b90320b064
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M accel/accel-system.c
    M include/qemu/accel.h
    M include/system/accel-ops.h
    M system/cpus.c
    M target/i386/whpx/whpx-accel-ops.c
    M target/i386/whpx/whpx-accel-ops.h
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  accel/system: Convert pre_resume() from AccelOpsClass to AccelClass

Accelerators call pre_resume() once. Since it isn't a method to
call for each vCPU, move it from AccelOpsClass to AccelClass.
Adapt WHPX.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250702185332.43650-21-phi...@linaro.org>


  Commit: e4a4163ed21e8d88f6a0c2d17f9487ad83841653
      
https://github.com/qemu/qemu/commit/e4a4163ed21e8d88f6a0c2d17f9487ad83841653
  Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M monitor/hmp-cmds-target.c

  Log Message:
  -----------
  monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()

Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be
logged by log_cpu_exec() in TCG. This flag was then used in commit
b227f6a8a7 to print RISC-V vector registers using this flag. Note that
this change was done in riscv_cpu_dump_state(), the cpu_dump_state()
callback for RISC-V, the same callback used in hmp_info_registers().

Back then we forgot to change hmp_info_registers(), and 'info registers'
isn't showing RISC-V vector registers as a result. No other target is
impacted since only RISC-V is using CPU_DUMP_VPU.

There's no reason to not show VPU regs in info_registers(), so add
CPU_DUMP_VPU to hmp_info_registers(). This will print vector registers
for all RISC-V machines and, as said above, has no impact in other
archs.

Cc: Dr. David Alan Gilbert <d...@treblig.org>
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20250623145306.991562-1-dbarb...@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>


  Commit: 431ac3b5d2b60c8bd8b34d417154060b9184dec1
      
https://github.com/qemu/qemu/commit/431ac3b5d2b60c8bd8b34d417154060b9184dec1
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add me as reviewer of overall accelerators section

I'd like to be informed of overall changes of accelerators.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-40-phi...@linaro.org>


  Commit: f9b0f69304071384b12912bf9dd78e9ffd261cec
      
https://github.com/qemu/qemu/commit/f9b0f69304071384b12912bf9dd78e9ffd261cec
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Fix SME vs AdvSIMD exception priority

We failed to raise an exception when
sme_excp_el == 0 and fp_excp_el == 1.

Cc: qemu-sta...@nongnu.org
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b4b2e070f41dd8774a70c6186141678558d79a38
      
https://github.com/qemu/qemu/commit/b4b2e070f41dd8774a70c6186141678558d79a38
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Fix sve_access_check for SME

Do not assume SME implies SVE.  Ensure that the non-streaming
check is present along the SME path, since it is not implied
by sme_*_enabled_check.

Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e6ffd009c7710a8cc98094897fa0af609c114683
      
https://github.com/qemu/qemu/commit/e6ffd009c7710a8cc98094897fa0af609c114683
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix 128-bit element ZIP, UZP, TRN

We missed the instructions UDEF when the vector size is too small.
We missed marking the instructions non-streaming with SME.

Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4f06e6eaeb2fe65b957be546c61ab2f11a87202c
      
https://github.com/qemu/qemu/commit/4f06e6eaeb2fe65b957be546c61ab2f11a87202c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode

  Log Message:
  -----------
  target/arm: Replace @rda_rn_rm_e0 in sve.decode

Replace @rda_rn_rm_e0 with @rda_rn_rm_ex, and require
users to supply an explicit esz.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c60a52fc576c9e2f5b8c26ed7b49ebd173b5c1e3
      
https://github.com/qemu/qemu/commit/c60a52fc576c9e2f5b8c26ed7b49ebd173b5c1e3
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix FMMLA (64-bit element) for 128-bit VL

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a827b94c67bab630499876e888f1ffe737d9f26b
      
https://github.com/qemu/qemu/commit/a827b94c67bab630499876e888f1ffe737d9f26b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Disable FEAT_F64MM if maximum SVE vector size too small

All F64MM instructions operate on a 256-bit vector.
If only 128-bit vectors is supported by the cpu,
then the cpu cannot enable F64MM.

Suggested-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3801c5b75ffc60957265513338e8fd5f8b6ce8a1
      
https://github.com/qemu/qemu/commit/3801c5b75ffc60957265513338e8fd5f8b6ce8a1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix PSEL size operands to tcg_gen_gvec_ands

Gvec only operates on size 8 and multiples of 16.
Predicates may be any multiple of 2.
Round up the size using the appropriate function.

Cc: qemu-sta...@nongnu.org
Fixes: 598ab0b24c0 ("target/arm: Implement PSEL")
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: cfc688c00ade84f6b32c7814b52c217f1d3b5eb1
      
https://github.com/qemu/qemu/commit/cfc688c00ade84f6b32c7814b52c217f1d3b5eb1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme_helper.c

  Log Message:
  -----------
  target/arm: Fix f16_dotadd vs nan selection

Implement FPProcessNaNs4 within f16_dotadd, rather than
simply letting NaNs propagate through the function.

Cc: qemu-sta...@nongnu.org
Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)")
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bf020eaa6741711902a425016e2c7585f222562d
      
https://github.com/qemu/qemu/commit/bf020eaa6741711902a425016e2c7585f222562d
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Fix bfdotadd_ebf vs nan selection

Implement FPProcessNaNs4 within bfdotadd_ebf, rather than
simply letting NaNs propagate through the function.

Cc: qemu-sta...@nongnu.org
Fixes: 0e1850182a1 ("target/arm: Implement FPCR.EBF=1 semantics for bfdotadd()")
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: afb1bd20df88edb553dbb70857a0b7f15c72c672
      
https://github.com/qemu/qemu/commit/afb1bd20df88edb553dbb70857a0b7f15c72c672
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Remove CPUARMState.vfp.scratch

The last use of this field was removed in b2fc7be972b9.

Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c994c84d384b87cd862d12f6b9db4bcfd42b5a7b
      
https://github.com/qemu/qemu/commit/c994c84d384b87cd862d12f6b9db4bcfd42b5a7b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/tcg/vfp_helper.c

  Log Message:
  -----------
  target/arm: Introduce FPST_ZA, FPST_ZA_F16

Rather than repeatedly copying FPST_FPCR to locals
and setting default nan mode, create dedicated float_status.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d74f0ceae557c35ee80bcc0afa20e4f95b6e3262
      
https://github.com/qemu/qemu/commit/d74f0ceae557c35ee80bcc0afa20e4f95b6e3262
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Use FPST_ZA for sme_fmopa_[hsd]

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 81123324a56fecce275a9995ddc1593e880b43ef
      
https://github.com/qemu/qemu/commit/81123324a56fecce275a9995ddc1593e880b43ef
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M linux-user/aarch64/signal.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/machine.c
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Rename zarray to za_state.za

The whole ZA state will also contain ZT0.
Make things easier in aarch64_set_svcr to zero both
by wrapping them in a common structure.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d8ff459b4021a4fdbd3bf0c4311bb24868188f0d
      
https://github.com/qemu/qemu/commit/d8ff459b4021a4fdbd3bf0c4311bb24868188f0d
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu-features.h
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar feature tests for SME2p1, SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b
      
https://github.com/qemu/qemu/commit/694b2625dd4ac1d6f4aa4dfc8ed7380ec843cd9b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Add ZT0

This is a 512-bit array introduced with SME2.
Save it only when ZA is in use.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3aad4bc8beb9a3a8c1ea3dc6ca9bfc85d3c7c8a4
      
https://github.com/qemu/qemu/commit/3aad4bc8beb9a3a8c1ea3dc6ca9bfc85d3c7c8a4
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Add zt0_excp_el to DisasContext

Pipe the value through from SMCR_ELx through hflags and into
the disassembly context.  Enable EZT0 in smcr_write.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 10f02d0ced4e15343fd234d5c6b0e6725a4f7f16
      
https://github.com/qemu/qemu/commit/10f02d0ced4e15343fd234d5c6b0e6725a4f7f16
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/syndrome.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 ZERO ZT0

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 83eae543efac1b2119eed5d888423fe9b87daa30
      
https://github.com/qemu/qemu/commit/83eae543efac1b2119eed5d888423fe9b87daa30
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-a64.h
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Add alignment argument to gen_sve_{ldr, str}

Honor AlignmentEnforced() for LDR/STR (vector),
(predicate), and (array vector).

Within the expansion functions, clear @align when we're
done emitting loads at the largest size.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-19-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 12511e2a7621d7e812ef76c4b6f0846ce494f5b1
      
https://github.com/qemu/qemu/commit/12511e2a7621d7e812ef76c4b6f0846ce494f5b1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 LDR/STR ZT0

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4fc8b7f4bcb7d16b02afb9ca1ddae538bba03c17
      
https://github.com/qemu/qemu/commit/4fc8b7f4bcb7d16b02afb9ca1ddae538bba03c17
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 MOVT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 51a64f1e772746ad0581a3b0d7637995fa608540
      
https://github.com/qemu/qemu/commit/51a64f1e772746ad0581a3b0d7637995fa608540
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Split get_tile_rowcol argument tile_index

Decode tile number and index offset beforehand and separately.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-22-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 2c43bee917bbb2c1844c30a21baaceee7874265c
      
https://github.com/qemu/qemu/commit/2c43bee917bbb2c1844c30a21baaceee7874265c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Rename MOVA for translate

Prepare for more kinds of MOVA from SME2 by renaming the
existing SME1 MOVA to indicate tile to/from vector.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-23-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 7afb9855fc81a0ac138b398aa645aff552d52ea5
      
https://github.com/qemu/qemu/commit/7afb9855fc81a0ac138b398aa645aff552d52ea5
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Split out get_zarray

Prepare for MOVA array to/from vector with multiple registers
by adding a div_len parameter, herein always 1, and a vec_mod
parameter, herein always 0.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-24-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c48d0471beb0cb197efda0b2be3fa75b4628a673
      
https://github.com/qemu/qemu/commit/c48d0471beb0cb197efda0b2be3fa75b4628a673
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Introduce ARMCPU.sme_max_vq

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-25-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 72cd08eb7614af79c7ef9fd66ff4e51352ad103b
      
https://github.com/qemu/qemu/commit/72cd08eb7614af79c7ef9fd66ff4e51352ad103b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Implement SME2 MOVA to/from tile, multiple registers

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-26-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e9de40e53821d4c2adbb115a412991b15cd59a76
      
https://github.com/qemu/qemu/commit/e9de40e53821d4c2adbb115a412991b15cd59a76
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Implement SME2 MOVA to/from array, multiple registers

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-27-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 24b5220f4c9d168b1acbbba71044d7848c90c8b5
      
https://github.com/qemu/qemu/commit/24b5220f4c9d168b1acbbba71044d7848c90c8b5
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 BMOPA

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-28-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e129ceae820a1b4dc1d10cc55ba98d421afe824a
      
https://github.com/qemu/qemu/commit/e129ceae820a1b4dc1d10cc55ba98d421afe824a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SMOPS, UMOPS (2-way)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-29-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: baf450ef83b27394358e294d2bd7f64899e0ef45
      
https://github.com/qemu/qemu/commit/baf450ef83b27394358e294d2bd7f64899e0ef45
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/gengvec64.c
    M target/arm/tcg/translate-a64.h
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Introduce gen_gvec_sve2_sqdmulh

To be used by both SVE2 and SME2.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-30-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bc65d2bd1cbffff6e0616a1417acf35ad2e10f29
      
https://github.com/qemu/qemu/commit/bc65d2bd1cbffff6e0616a1417acf35ad2e10f29
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-a64.c
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/helper.h
    M target/arm/tcg/neon_helper.c
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement SME2 Multiple and Single SVE Destructive

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-31-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 930760eb753d3beead00920cbb0187f755c06dd9
      
https://github.com/qemu/qemu/commit/930760eb753d3beead00920cbb0187f755c06dd9
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 Multiple Vectors SVE Destructive

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-32-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d636130fbba61956d49a139c5690c3dc569dfb9a
      
https://github.com/qemu/qemu/commit/d636130fbba61956d49a139c5690c3dc569dfb9a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-33-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9fbc9bd4861971b717181872ec9c578b42f5bcf8
      
https://github.com/qemu/qemu/commit/9fbc9bd4861971b717181872ec9c578b42f5bcf8
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 ADD/SUB (array results, multiple vectors)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-34-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a476ef9652793f1932605737adb8bce89ee069b2
      
https://github.com/qemu/qemu/commit/a476ef9652793f1932605737adb8bce89ee069b2
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s

Indicate whether to use FPST_FPCR or FPST_ZA via bit 2 of
simd_data(desc).  For SVE, this bit remains zero.
For do_FMLAL_zzzw, this requires no change.
For do_FMLAL_zzxw, move the index up one bit.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-35-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 04afb926711924b41a84058851f285460ccb16c8
      
https://github.com/qemu/qemu/commit/04afb926711924b41a84058851f285460ccb16c8
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Add helper_gvec{_ah}_bfmlsl{_nx}

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-36-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 50548277bd1be465bb7e8e575d67d20836552e31
      
https://github.com/qemu/qemu/commit/50548277bd1be465bb7e8e575d67d20836552e31
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 FMLAL, BFMLAL

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-37-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 05cad66f103f4ac0d937d31ada5dcd5a550e6304
      
https://github.com/qemu/qemu/commit/05cad66f103f4ac0d937d31ada5dcd5a550e6304
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SME2 FDOT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-38-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: be0b56851a56da8ef4410cd936a351bd4070caaa
      
https://github.com/qemu/qemu/commit/be0b56851a56da8ef4410cd936a351bd4070caaa
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 BFDOT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-39-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 7bca70e01a3b2e89b265254a468ecc3c150eade9
      
https://github.com/qemu/qemu/commit/7bca70e01a3b2e89b265254a468ecc3c150eade9
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/helper.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SME2 FVDOT, BFVDOT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-40-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f7186b4288d88c529c5cb3eb813146092a37cfce
      
https://github.com/qemu/qemu/commit/f7186b4288d88c529c5cb3eb813146092a37cfce
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate-neon.c
    M target/arm/tcg/translate-sve.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh]

Emphasize that these are 4-way dot products.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-41-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9fce675a8e3c216db3a9dd029d4e655295125110
      
https://github.com/qemu/qemu/commit/9fce675a8e3c216db3a9dd029d4e655295125110
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-42-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a49089cd60667123cfdb949a8bd0b672575d0eb2
      
https://github.com/qemu/qemu/commit/a49089cd60667123cfdb949a8bd0b672575d0eb2
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Rename SVE SDOT and UDOT patterns

Emphasize the 4-way nature of these dot products.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-43-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 050ce4fb6468d485cb906e0315eb8725266f5b0e
      
https://github.com/qemu/qemu/commit/050ce4fb6468d485cb906e0315eb8725266f5b0e
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Tighten USDOT (vectors) decode

Rename to USDOT_zzzz_4s and force size=2 during decode.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-44-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 26c3bafbf355f8aa8cb9197ccc4136c878c8bbfb
      
https://github.com/qemu/qemu/commit/26c3bafbf355f8aa8cb9197ccc4136c878c8bbfb
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-45-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 279cd4d3123b52764c5e320b0e5a41b6cf7b4510
      
https://github.com/qemu/qemu/commit/279cd4d3123b52764c5e320b0e5a41b6cf7b4510
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-46-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0a151896ebba73b1fa75bbfdbf25a2f32e09fa19
      
https://github.com/qemu/qemu/commit/0a151896ebba73b1fa75bbfdbf25a2f32e09fa19
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-47-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e0646fc93e40d32462ee2b87be187e088dba8593
      
https://github.com/qemu/qemu/commit/e0646fc93e40d32462ee2b87be187e088dba8593
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/translate-neon.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix

Emphasize the non-fused nature of these multiply-add.
Matches other helpers such as gvec_rsqrts_nf_[hs].

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-48-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 77a15fa72a0e9b0d5d78da0a482c57edcac67216
      
https://github.com/qemu/qemu/commit/77a15fa72a0e9b0d5d78da0a482c57edcac67216
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 FMLA, FMLS

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-49-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 57ef00819ef46188f803e4f59382044c75073d34
      
https://github.com/qemu/qemu/commit/57ef00819ef46188f803e4f59382044c75073d34
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SME2 BFMLA, BFMLS

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-50-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c4f514e2b005038d4bb9edc14b3878632f043458
      
https://github.com/qemu/qemu/commit/c4f514e2b005038d4bb9edc14b3878632f043458
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-51-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ccb512d5b504d21ab59c28e3e41757b88779c890
      
https://github.com/qemu/qemu/commit/ccb512d5b504d21ab59c28e3e41757b88779c890
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 ADD/SUB (array accumulator)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-52-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 465d36db0e12cf9eb8a08e3ba1c6b306f356ba52
      
https://github.com/qemu/qemu/commit/465d36db0e12cf9eb8a08e3ba1c6b306f356ba52
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-53-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f73ef7f90f5c99111383f1005c0d7c72d9cb9247
      
https://github.com/qemu/qemu/commit/f73ef7f90f5c99111383f1005c0d7c72d9cb9247
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement SME2 FCVT (widening), FCVTL

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-54-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 91a11f74683f7a873be5908601999239fb7ba363
      
https://github.com/qemu/qemu/commit/91a11f74683f7a873be5908601999239fb7ba363
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 FCVTZS, FCVTZU

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-55-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 41167be4290124052f28d719994572269d7b3ec1
      
https://github.com/qemu/qemu/commit/41167be4290124052f28d719994572269d7b3ec1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SCVTF, UCVTF

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-56-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 2065b1420d701b95dfed7e9d76bf7f011c3da9b3
      
https://github.com/qemu/qemu/commit/2065b1420d701b95dfed7e9d76bf7f011c3da9b3
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-57-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 88b73373110bbc60c9d5238fd387d213e91933af
      
https://github.com/qemu/qemu/commit/88b73373110bbc60c9d5238fd387d213e91933af
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Introduce do_[us]sat_[bhs] macros

Inputs are a wider type of indeterminate sign.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-58-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 63b2c8de713933f42f1999cd003f12f90bdc5249
      
https://github.com/qemu/qemu/commit/63b2c8de713933f42f1999cd003f12f90bdc5249
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Use do_[us]sat_[bhs] in sve_helper.c

Replace and remove do_sat_bhs.
This avoids multiple repetitions of INT*_MIN/MAX.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-59-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bde57978ce3794b8ebaab99307a4899cf4bedd55
      
https://github.com/qemu/qemu/commit/bde57978ce3794b8ebaab99307a4899cf4bedd55
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-60-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 10168d3912d46d075724dd485aee5eabced7b99f
      
https://github.com/qemu/qemu/commit/10168d3912d46d075724dd485aee5eabced7b99f
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-61-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 2ccea621573dd8c2aa23583947d598fe8382b93c
      
https://github.com/qemu/qemu/commit/2ccea621573dd8c2aa23583947d598fe8382b93c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SUNPK, UUNPK

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-62-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a3a019c0efc06e63c648c416484ed5083678c93d
      
https://github.com/qemu/qemu/commit/a3a019c0efc06e63c648c416484ed5083678c93d
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 ZIP, UZP (four registers)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-63-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9a7d445c09aa79a14bc4c5eede635b043622cbf0
      
https://github.com/qemu/qemu/commit/9a7d445c09aa79a14bc4c5eede635b043622cbf0
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/mve_helper.c
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Move do_urshr, do_srshr to vec_internal.h

Unify two copies of these inline functions.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-64-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 70ad5b9fb172709d1e8bb8718c4e180e46967b8b
      
https://github.com/qemu/qemu/commit/70ad5b9fb172709d1e8bb8718c4e180e46967b8b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-65-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 7e27088cfc3506c402ea50198cc317315258cadd
      
https://github.com/qemu/qemu/commit/7e27088cfc3506c402ea50198cc317315258cadd
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 ZIP, UZP (two registers)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-66-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 8b61eff8e72fee0d5b0cb937674d77fc99674e6c
      
https://github.com/qemu/qemu/commit/8b61eff8e72fee0d5b0cb937674d77fc99674e6c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-67-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c1317025d83a298be82a2d05586a6a23684ad877
      
https://github.com/qemu/qemu/commit/c1317025d83a298be82a2d05586a6a23684ad877
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Enable SCLAMP, UCLAMP for SVE2p1

These instructions are present in both SME(1) and SVE2.1 extensions.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-68-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e9b743947b154b51dad778e31e323c8ef3133a52
      
https://github.com/qemu/qemu/commit/e9b743947b154b51dad778e31e323c8ef3133a52
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement FCLAMP for SME2, SVE2p1

This is the single vector version within SVE decode space.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-69-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f8f65ebc0ab747cd233ace17318b268593f56910
      
https://github.com/qemu/qemu/commit/f8f65ebc0ab747cd233ace17318b268593f56910
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2p1 Multiple Zero

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-70-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bcbe82a29396e9f007e1575da0bb4e7e57451c71
      
https://github.com/qemu/qemu/commit/bcbe82a29396e9f007e1575da0bb4e7e57451c71
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Introduce pred_count_test

For WHILE, we have the count of enabled predicates, so we don't
need to search to compute the PredTest result.  Reuse the logic
that will shortly be required for counted predicates.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-71-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 18914dfba78e64148219ba9611b0019c0a81ff52
      
https://github.com/qemu/qemu/commit/18914dfba78e64148219ba9611b0019c0a81ff52
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Fold predtest_ones into helper_sve_brkns

Merge predtest_ones into its only caller.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-72-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 91afd009bab55b0b479e6fb0aadc9366e9bd6209
      
https://github.com/qemu/qemu/commit/91afd009bab55b0b479e6fb0aadc9366e9bd6209
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Expand do_zero inline

Expand to memset plus the return value, when used.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-73-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 56ddef77944b4441f199b5e15c8fc1a058fd3335
      
https://github.com/qemu/qemu/commit/56ddef77944b4441f199b5e15c8fc1a058fd3335
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Split out do_whilel from helper_sve_whilel

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-74-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3fd8ce429447db5d1c1302887c68bc23a73a8a81
      
https://github.com/qemu/qemu/commit/3fd8ce429447db5d1c1302887c68bc23a73a8a81
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Split out do_whileg from helper_sve_whileg

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250704142112.1018902-75-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f96fd13c6ea030871e114c0d274e61d0cd5ff3ca
      
https://github.com/qemu/qemu/commit/f96fd13c6ea030871e114c0d274e61d0cd5ff3ca
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Move scale by esz into helper_sve_while*

Change the API to pass element count rather than bit count.
This will be helpful later for predicate as counter.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-76-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 54e260bbfc3fb4c6817d9a2457bdc9ef4d142f3a
      
https://github.com/qemu/qemu/commit/54e260bbfc3fb4c6817d9a2457bdc9ef4d142f3a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Split trans_WHILE to lt and gt

Use TRANS_FEAT to select the correct predicate.
Pass the helper and a boolean to do_WHILE.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-77-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b61f4530535a483688e76a925f6203fa22e332e8
      
https://github.com/qemu/qemu/commit/b61f4530535a483688e76a925f6203fa22e332e8
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Enable PSEL for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-78-richard.hender...@linaro.org
This instruction is present in both SME(1) and SVE2.1 extensions.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a3dde8e382cd90e5b48c363255bd9d8ef31d4232
      
https://github.com/qemu/qemu/commit/a3dde8e382cd90e5b48c363255bd9d8ef31d4232
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2p1 WHILE (predicate pair)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-79-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f9cb0ac8ba387f7da6153d39d77b24271eb7d49c
      
https://github.com/qemu/qemu/commit/f9cb0ac8ba387f7da6153d39d77b24271eb7d49c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2p1 WHILE (predicate as counter)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-80-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b7094bc2528ee310ccabc05a494fe68ce9c06ce7
      
https://github.com/qemu/qemu/commit/b7094bc2528ee310ccabc05a494fe68ce9c06ce7
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2p1 PTRUE (predicate as counter)

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-81-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 8f7e127b66d0e51b3940c779695bc698138060d4
      
https://github.com/qemu/qemu/commit/8f7e127b66d0e51b3940c779695bc698138060d4
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-82-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 16fe3bb942e80ae0a2cd0690629bb73cc131092b
      
https://github.com/qemu/qemu/commit/16fe3bb942e80ae0a2cd0690629bb73cc131092b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement SVE2p1 PEXT

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-83-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ab6bf3d93d3296b46c106c5867db09e9d3bd8880
      
https://github.com/qemu/qemu/commit/ab6bf3d93d3296b46c106c5867db09e9d3bd8880
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 SEL

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-84-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 5b334d17e639799904b2aa873b9cbd7c08b7ab8f
      
https://github.com/qemu/qemu/commit/5b334d17e639799904b2aa873b9cbd7c08b7ab8f
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-85-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 1de7ecfc12d05d5c7929c22ccdaf7c834f6f2305
      
https://github.com/qemu/qemu/commit/1de7ecfc12d05d5c7929c22ccdaf7c834f6f2305
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-86-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4fddbdf934937d0043d0601262809df14bd14abb
      
https://github.com/qemu/qemu/commit/4fddbdf934937d0043d0601262809df14bd14abb
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-87-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 47810f99e846501c817fb77ebd03b6914342f7e5
      
https://github.com/qemu/qemu/commit/47810f99e846501c817fb77ebd03b6914342f7e5
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-88-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a4a49a31f499adb8ba2fca6b048d4f51f41e178a
      
https://github.com/qemu/qemu/commit/a4a49a31f499adb8ba2fca6b048d4f51f41e178a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement DUPQ for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-89-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3b5257c8602b3002540c4dbdd3929251bd3acc85
      
https://github.com/qemu/qemu/commit/3b5257c8602b3002540c4dbdd3929251bd3acc85
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement EXTQ for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-90-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e421e4e9727c2b835a09b9d43777f3a56b252899
      
https://github.com/qemu/qemu/commit/e421e4e9727c2b835a09b9d43777f3a56b252899
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement PMOV for SME2p1/SVE2p1

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-91-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 945a379438736571d9bb6086f1e264452c5427f1
      
https://github.com/qemu/qemu/commit/945a379438736571d9bb6086f1e264452c5427f1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-92-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 47f4cdd6c28755c7f1415ac38bc3350afaaee330
      
https://github.com/qemu/qemu/commit/47f4cdd6c28755c7f1415ac38bc3350afaaee330
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-93-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b0b0818a4a41ab10f1bd5fb5e2c0cd815ae3fee9
      
https://github.com/qemu/qemu/commit/b0b0818a4a41ab10f1bd5fb5e2c0cd815ae3fee9
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SME2 counted predicate register load/store

Implement the SVE2p1 consecutive register LD1/ST1,
and the SME2 strided register LD1/ST1.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-94-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0af0c9bbb94b5049354cd7a102929b1fbf097c20
      
https://github.com/qemu/qemu/commit/0af0c9bbb94b5049354cd7a102929b1fbf097c20
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sve.decode

  Log Message:
  -----------
  target/arm: Split the ST_zpri and ST_zprr patterns

The msz > esz encodings are reserved, and some of
them are about to be reused.  Split these patterns
so that the new insns do not overlap.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-95-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: fc5f060bcb7b45d8e330e294947cac7dffa0ea82
      
https://github.com/qemu/qemu/commit/fc5f060bcb7b45d8e330e294947cac7dffa0ea82
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/sve_ldst_internal.h
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-96-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 697fe75202f56135b74940ec41deecd3357bda23
      
https://github.com/qemu/qemu/commit/697fe75202f56135b74940ec41deecd3357bda23
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/sve_ldst_internal.h

  Log Message:
  -----------
  target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h

Move from sme_helper.c to the shared header.
Add a comment noting the lack of atomicity.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-97-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0e4ba0607b74c82525dcfc6ed1c4b89bb4cbb39b
      
https://github.com/qemu/qemu/commit/0e4ba0607b74c82525dcfc6ed1c4b89bb4cbb39b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-98-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d2aa9a804ee678f0327bc5c6018a814caa424b77
      
https://github.com/qemu/qemu/commit/d2aa9a804ee678f0327bc5c6018a814caa424b77
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement LD1Q, ST1Q for SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-99-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ec2d9709653f5c0c5503f177e5cdf6ba3e8f2627
      
https://github.com/qemu/qemu/commit/ec2d9709653f5c0c5503f177e5cdf6ba3e8f2627
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement MOVAZ for SME2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-100-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a19b104f849a0ab6f781755f76e567960629a69c
      
https://github.com/qemu/qemu/commit/a19b104f849a0ab6f781755f76e567960629a69c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-101-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 960bf1a032d1edbff6b1f2ea716e6e8d539e3468
      
https://github.com/qemu/qemu/commit/960bf1a032d1edbff6b1f2ea716e6e8d539e3468
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Rename FMOPA_h to FMOPA_w_h

The pattern we currently have as FMOPA_h is the "widening" insn
that takes fp16 inputs and produces single-precision outputs.
This is unlike FMOPA_s and FMOPA_d, which are non-widening
produce outputs the same size as their inputs.

SME2 introduces a non-widening fp16 FMOPA operation; rename
FMOPA_h to FMOPA_w_h (for 'widening'), so we can use FMOPA_h
for the non-widening version, giving it a name in line with
the other non-widening ops FMOPA_s and FMOPA_d.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-102-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 99548ad2475435bd73dc6dfb008475c1b670fe2a
      
https://github.com/qemu/qemu/commit/99548ad2475435bd73dc6dfb008475c1b670fe2a
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Rename BFMOPA to BFMOPA_w

Our current BFMOPA opcode pattern is the widening version
of the insn. Rename it to BFMOPA_w, to make way for
the non-widening version added in SME2.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-103-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: eba6a6f88279f00525bc9f35d758ba0f163fc9f8
      
https://github.com/qemu/qemu/commit/eba6a6f88279f00525bc9f35d758ba0f163fc9f8
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/vec_internal.h

  Log Message:
  -----------
  target/arm: Support FPCR.AH in SME FMOPS, BFMOPS

For non-widening, we can use float_muladd_negate_product,
For widening, which uses dot-product, we need to handle
the negation explicitly.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-104-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 1a039f94d355b615237221c72b81fe6bd2018210
      
https://github.com/qemu/qemu/commit/1a039f94d355b615237221c72b81fe6bd2018210
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement FMOPA (non-widening) for fp16

Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-105-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4805911a925ffbf798b29dce50cbb9585fd8e87e
      
https://github.com/qemu/qemu/commit/4805911a925ffbf798b29dce50cbb9585fd8e87e
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/translate-sme.c

  Log Message:
  -----------
  target/arm: Implement SME2 BFMOPA (non-widening)

Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-106-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 7b1613a1020d294219867a2cad6b41c46acec8f2
      
https://github.com/qemu/qemu/commit/7b1613a1020d294219867a2cad6b41c46acec8f2
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Enable FEAT_SME2p1 on -cpu max

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-107-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 083fef73585dfa03f72055ace6de8dec4912d0b0
      
https://github.com/qemu/qemu/commit/083fef73585dfa03f72055ace6de8dec4912d0b0
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-07-04 (Fri, 04 Jul 2025)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250704142112.1018902-108-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 84d1639f286fed00f8a48f417992afc80af48426
      
https://github.com/qemu/qemu/commit/84d1639f286fed00f8a48f417992afc80af48426
  Author: Stefan Hajnoczi <stefa...@redhat.com>
  Date:   2025-07-07 (Mon, 07 Jul 2025)

  Changed paths:
    M accel/accel-system.c
    M accel/hvf/hvf-all.c
    M accel/tcg/tcg-accel-ops-mttcg.c
    M accel/tcg/tcg-accel-ops-rr.c
    M accel/tcg/tcg-accel-ops.c
    M include/qemu/accel.h
    M include/system/accel-ops.h
    M system/cpus.c
    M target/i386/whpx/whpx-accel-ops.c
    M target/i386/whpx/whpx-accel-ops.h
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  Merge tag 'accel-20250704' of https://github.com/philmd/qemu into staging

Accelerators patches

- Generic API consolidation, cleanups (dead code removal, documentation added)
- Remove monitor TCG 'info opcount' and @x-query-opcount
- Have HVF / NVMM / WHPX use generic CPUState::vcpu_dirty field
- Expose nvmm_enabled() and whpx_enabled() to common code
- Report missing com.apple.security.hypervisor entitlement
- Have hmp_info_registers() dump vector registers

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[full]
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* tag 'accel-20250704' of https://github.com/philmd/qemu: (35 commits)
  MAINTAINERS: Add me as reviewer of overall accelerators section
  monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()
  accel/system: Convert pre_resume() from AccelOpsClass to AccelClass
  accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
  accel: Remove unused MachineState argument of AccelClass::setup_post()
  accel: Directly pass AccelState argument to AccelClass::has_memory()
  accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()
  accel/kvm: Prefer local AccelState over global MachineState::accel
  accel/tcg: Prefer local AccelState over global current_accel()
  accel/hvf: Re-use QOM allocated state
  accel: Propagate AccelState to AccelClass::init_machine()
  accel: Keep reference to AccelOpsClass in AccelClass
  accel: Expose and register generic_handle_interrupt()
  accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
  accel/whpx: Expose whpx_enabled() to common code
  accel/nvmm: Expose nvmm_enabled() to common code
  accel/system: Document cpu_synchronize_state_post_init/reset()
  accel/system: Document cpu_synchronize_state()
  accel/kvm: Remove kvm_cpu_synchronize_state() stub
  accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field
  ...

Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>

Conflicts:
  accel/accel-system.c
  accel/hvf/hvf-all.c
  include/qemu/accel.h

  pre_resume_vm()-related conflicts.


  Commit: df6fe2abf2e990f767ce755d426bc439c7bba336
      
https://github.com/qemu/qemu/commit/df6fe2abf2e990f767ce755d426bc439c7bba336
  Author: Stefan Hajnoczi <stefa...@redhat.com>
  Date:   2025-07-07 (Mon, 07 Jul 2025)

  Changed paths:
    M docs/about/deprecated.rst
    M docs/system/arm/emulation.rst
    M hw/arm/highbank.c
    M linux-user/aarch64/signal.c
    M linux-user/elfload.c
    M target/arm/cpu-features.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/machine.c
    M target/arm/syndrome.h
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/gengvec64.c
    M target/arm/tcg/helper-a64.c
    M target/arm/tcg/helper-sme.h
    M target/arm/tcg/helper-sve.h
    M target/arm/tcg/helper.h
    M target/arm/tcg/hflags.c
    M target/arm/tcg/m_helper.c
    M target/arm/tcg/mve_helper.c
    M target/arm/tcg/neon_helper.c
    M target/arm/tcg/sme.decode
    M target/arm/tcg/sme_helper.c
    M target/arm/tcg/sve.decode
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/sve_ldst_internal.h
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate-a64.h
    M target/arm/tcg/translate-neon.c
    M target/arm/tcg/translate-sme.c
    M target/arm/tcg/translate-sve.c
    M target/arm/tcg/translate.h
    M target/arm/tcg/vec_helper.c
    M target/arm/tcg/vec_internal.h
    M target/arm/tcg/vfp_helper.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into 
staging

target-arm queue:
 * Implement emulation of SME2p1 and SVE2p1
 * Correctly enforce alignment checks for v8M loads and
   stores done via helper functions
 * Mark the "highbank" and the "midway" machine as deprecated

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# gpg:                issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmayd...@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
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* tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu: (119 commits)
  linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1
  target/arm: Enable FEAT_SME2p1 on -cpu max
  target/arm: Implement SME2 BFMOPA (non-widening)
  target/arm: Implement FMOPA (non-widening) for fp16
  target/arm: Support FPCR.AH in SME FMOPS, BFMOPS
  target/arm: Rename BFMOPA to BFMOPA_w
  target/arm: Rename FMOPA_h to FMOPA_w_h
  target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1
  target/arm: Implement MOVAZ for SME2p1
  target/arm: Implement LD1Q, ST1Q for SVE2p1
  target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1
  target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h
  target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1
  target/arm: Split the ST_zpri and ST_zprr patterns
  target/arm: Implement SME2 counted predicate register load/store
  target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1
  target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1
  target/arm: Implement PMOV for SME2p1/SVE2p1
  target/arm: Implement EXTQ for SME2p1/SVE2p1
  target/arm: Implement DUPQ for SME2p1/SVE2p1
  ...

Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>


Compare: https://github.com/qemu/qemu/compare/e240f6cc2591...df6fe2abf2e9

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