Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2dad56b50d895925cd5b687bce444e90b7c132ae
https://github.com/qemu/qemu/commit/2dad56b50d895925cd5b687bce444e90b7c132ae
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Use mmu idx bitmap method when flush TLB
With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used
rather than itself. Also bitmap of MMU_KERNEL_IDX and MMU_USER_IDX are
used rather than that of current running mmu idx when flush TLB.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 5a1d5dbccc6af262419bce69068b3cb1a1ffdb4a
https://github.com/qemu/qemu/commit/5a1d5dbccc6af262419bce69068b3cb1a1ffdb4a
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add parameter tlb pointer with fill_tlb_entry
With function fill_tlb_entry(), it will update LoongArch emulated
TLB information. Here parameter tlb pointer is added so that TLB
entry will be updated based on relative TLB CSR registers.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 8fa3df98336ca2872dc51a8859142e8892844fb6
https://github.com/qemu/qemu/commit/8fa3df98336ca2872dc51a8859142e8892844fb6
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Reduce TLB flush with helper_tlbwr
With function helper_tlbwr(), specified LoongArch TLB entry will be
updated. There are two PTE pages in one TLB entry called even/odd
pages. Supposing even/odd page is normal/none state, when odd page
is added, TLB entry is changed as normal/normal state and even page
keeps unchanged.
In this situation, it is not necessary to flush QEMU TLB since even
page keep unchanged and odd page is newly changed. Here check whether
PTE page is the same or not, TLB flush can be skipped if both are the
same or newly added.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 349f3ec027cffc14ca6d7f83e2618714c7054a07
https://github.com/qemu/qemu/commit/349f3ec027cffc14ca6d7f83e2618714c7054a07
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Update TLB index selection method
With function helper_tlbfill(), since there is no suitable TLB entry,
new TLB will be added and flush one old TLB entry. The old TLB entry
index is selected randomly now, instead it can be optimized as
following:
1. invalid TLB entry can be selected at first.
2. TLB entry with other ASID can be selected secondly
3. random method is used by last.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 27a26b48bfb71af85a9cf67d8702ecef31650653
https://github.com/qemu/qemu/commit/27a26b48bfb71af85a9cf67d8702ecef31650653
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tcg/csr_helper.c
Log Message:
-----------
target/loongarch: Fix page size set issue with CSR_STLBPS
When modify register CSR_STLBPS, the page size should come from
input parameter rather than old value.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: e49d914ceec98a52e67438a8259768482ace639c
https://github.com/qemu/qemu/commit/e49d914ceec98a52e67438a8259768482ace639c
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add tlb search callback in loongarch_tlb_search()
With function loongarch_tlb_search(), it is to search TLB entry with
speficied virtual address, the difference is selection with asid and
global bit. Here add selection callback with asid and global bit.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 58c5522f1736404e6e6d396c1601ad3a1b15d7ed
https://github.com/qemu/qemu/commit/58c5522f1736404e6e6d396c1601ad3a1b15d7ed
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add common API loongarch_tlb_search_cb()
Common API loongarch_tlb_search_cb() is added here to search TLB entry
with specified address.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 5e3ccedcf925ad4913baa953d05933df1f78e9ed
https://github.com/qemu/qemu/commit/5e3ccedcf925ad4913baa953d05933df1f78e9ed
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Change return value type with loongarch_tlb_search_cb()
With function loongarch_tlb_search_cb(), change return value type from
bool type to pointer LoongArchTLB *, the pointer type can be use directly
in future.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 96e654cf3e6e03d61de447ad7117f53ed2bff998
https://github.com/qemu/qemu/commit/96e654cf3e6e03d61de447ad7117f53ed2bff998
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g
With function helper_invtlb_page_asid_or_g(), currently it is to
search TLB entry one by one. Instead STLB can be searched at first
with hash method, and then search MTLB with one by one method.
Here common API loongarch_tlb_search_cb() is used in function
helper_invtlb_page_asid_or_g().
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: eae570bdcd2d22c0e4bc058faff7f5ff874cb801
https://github.com/qemu/qemu/commit/eae570bdcd2d22c0e4bc058faff7f5ff874cb801
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid
With function helper_invtlb_page_asid(), currently it is to search
TLB entry one by one. Instead STLB can be searched at first with hash
method, and then search MTLB with one by one method
Here common API loongarch_tlb_search_cb() is used in function
helper_invtlb_page_asid()
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 56db997db04b14c15fbfbdaaa5eb924c53b730fa
https://github.com/qemu/qemu/commit/56db997db04b14c15fbfbdaaa5eb924c53b730fa
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Invalid tlb entry in invalidate_tlb()
Invalid tlb entry in function invalidate_tlb(), and its usage is
simple and easy to use.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 66746876fed5eb3c04c2f958bef927df3389d42c
https://github.com/qemu/qemu/commit/66746876fed5eb3c04c2f958bef927df3389d42c
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()
With function helper_invtlb_page_asid_or_g(), only one TLB entry in
LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
necessary to flush all QEMU TLB, only flush address range specified
LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
so that only QEMU TLB entry with specified address range is flushed.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 8d26856fabf8faac60de03a2e0fc35e5338e248e
https://github.com/qemu/qemu/commit/8d26856fabf8faac60de03a2e0fc35e5338e248e
Author: Bibo Mao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()
With function helper_invtlb_page_asid(), only one TLB entry in
LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
necessary to flush all QEMU TLB, only flush address range specified
LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
so that only QEMU TLB entry with specified address range is flushed.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: caf1704c56a38dbd032fd0174c07eded3a624072
https://github.com/qemu/qemu/commit/caf1704c56a38dbd032fd0174c07eded3a624072
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M include/hw/loongarch/virt.h
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: move some machine define to virt.h
move some machine define to virt.h
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 2002711e3dec0f0bb3eb86ee1e108ec9e95ed46f
https://github.com/qemu/qemu/commit/2002711e3dec0f0bb3eb86ee1e108ec9e95ed46f
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
hw/loongarch: add virt feature dmsi support
dmsi feature is added in LoongArchVirtMachinState, and it is used
to check whether virt machine supports the directy Message-Interrupts.
and by default set dmsi with ON_OFF_AUTO_AUTO.
LoongArchVirtMachineState adds misc_feature and misc_status for misc
features and status. and set the default dintc feature bit.
Msgint feature is added in LoongArchCPU, and it is used to check
whether th cpu supports the Message-Interrupts and by default set
mesgint with ON_OFF_AUTO_AUTO.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 86f4c80ab4a0d7a76d000515425d025004d6cd8b
https://github.com/qemu/qemu/commit/86f4c80ab4a0d7a76d000515425d025004d6cd8b
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch: add misc register support dmsi
Add feature register and misc register for dmsi feature checking and
setting
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 4d4baab24179b51072f5e182aa41d44306ed593c
https://github.com/qemu/qemu/commit/4d4baab24179b51072f5e182aa41d44306ed593c
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/Kconfig
A hw/intc/loongarch_dintc.c
M hw/intc/meson.build
M hw/loongarch/Kconfig
A include/hw/intc/loongarch_dintc.h
Log Message:
-----------
loongarch: add a direct interrupt controller device
Add Loongarch direct interrupt controller device base Definition.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 3ff989d566ec880a5d06de7bb65d3dc35fc3b63b
https://github.com/qemu/qemu/commit/3ff989d566ec880a5d06de7bb65d3dc35fc3b63b
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/cpu.h
M target/loongarch/machine.c
Log Message:
-----------
target/loongarch: add msg interrupt CSR registers
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Reviewed-by: Bibo Mao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Message-ID: <[email protected]>
Commit: 07f3e5203ade3fd2e3d8d0593bcdb0aa39e022d4
https://github.com/qemu/qemu/commit/07f3e5203ade3fd2e3d8d0593bcdb0aa39e022d4
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/loongarch_dintc.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_dintc.h
M include/hw/loongarch/virt.h
M include/hw/pci-host/ls7a.h
Log Message:
-----------
hw/loongarch: DINTC add a MemoryRegion
the DINTC use [2fe00000-2ff00000) Memory.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 386aef3e4a7fbfb8c051f8c24832492288fe6185
https://github.com/qemu/qemu/commit/386aef3e4a7fbfb8c051f8c24832492288fe6185
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/loongarch_dintc.c
M target/loongarch/cpu.h
Log Message:
-----------
hw/loongarch: Implement dintc realize and unrealize
Implement th DINTC realize and unrealize.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Commit: 0d148eaf5a3eb14469b536e37bb1936fd0085f03
https://github.com/qemu/qemu/commit/0d148eaf5a3eb14469b536e37bb1936fd0085f03
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/loongarch_dintc.c
Log Message:
-----------
hw/loongarch: Implement dintc set irq
Implement dintc set irq and update CSR_MSGIS.
Reviewed-by: Bibo Mao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Message-ID: <[email protected]>
Commit: c2396bfd4892091032a482118895a02ac87ab3e0
https://github.com/qemu/qemu/commit/c2396bfd4892091032a482118895a02ac87ab3e0
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/cpu-csr.h
Log Message:
-----------
target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts.
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for DINTC irq.
Reviewed-by: Bibo Mao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Message-ID: <[email protected]>
Commit: ce47eaadbd6acb466095465049f8433459b022a8
https://github.com/qemu/qemu/commit/ce47eaadbd6acb466095465049f8433459b022a8
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/csr.c
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
Log Message:
-----------
target/loongarch:Implement csrrd CSR_MSGIR register
implement the read-clear feature for CSR_MSGIR register.
Reviewed-by: Bibo Mao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Message-ID: <[email protected]>
Commit: 7470657ec157d4526752147165b2d368e2c7002e
https://github.com/qemu/qemu/commit/7470657ec157d4526752147165b2d368e2c7002e
Author: Song Gao <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/loongarch_dintc.c
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch: Implement DINTC plug/unplug interfaces
when cpu added, connect dintc irq to cpu INT_DMSI irq pin.
Reviewed-by: Bibo Mao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Message-ID: <[email protected]>
Commit: 7b59aa146a1e4c501f8f7252a39d6691788f183e
https://github.com/qemu/qemu/commit/7b59aa146a1e4c501f8f7252a39d6691788f183e
Author: Richard Henderson <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/Kconfig
A hw/intc/loongarch_dintc.c
M hw/intc/meson.build
M hw/loongarch/Kconfig
M hw/loongarch/virt.c
A include/hw/intc/loongarch_dintc.h
M include/hw/loongarch/virt.h
M include/hw/pci-host/ls7a.h
M target/loongarch/cpu-csr.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/csr.c
M target/loongarch/machine.c
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
Log Message:
-----------
Merge tag 'pull-loongarch-20250928' of https://github.com/gaosong715/qemu
into staging
pull-loongarch-20250928
v2: fix build win64 errors.
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# Fn06A/0SQKLVcktq2lX+aRurdGw/LKt/1mtSFJes6s5VVCrNuFFzmkXzjs/m0CcX
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# gpg: Signature made Sun 28 Sep 2025 02:42:53 AM PDT
# gpg: using RSA key CA473C44D6A09C189A193FCD452B96852B268216
# gpg: Good signature from "Song Gao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CA47 3C44 D6A0 9C18 9A19 3FCD 452B 9685 2B26 8216
* tag 'pull-loongarch-20250928' of https://github.com/gaosong715/qemu:
hw/loongarch: Implement DINTC plug/unplug interfaces
target/loongarch:Implement csrrd CSR_MSGIR register
target/loongarch: Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for msg interrupts.
hw/loongarch: Implement dintc set irq
hw/loongarch: Implement dintc realize and unrealize
hw/loongarch: DINTC add a MemoryRegion
target/loongarch: add msg interrupt CSR registers
loongarch: add a direct interrupt controller device
hw/loongarch: add misc register support dmsi
hw/loongarch: add virt feature dmsi support
target/loongarch: move some machine define to virt.h
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4975b64efb5aa4248cbc3760312bbe08d6e71638
https://github.com/qemu/qemu/commit/4975b64efb5aa4248cbc3760312bbe08d6e71638
Author: Richard Henderson <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu into
staging
loongarch queue
# -----BEGIN PGP SIGNATURE-----
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# 8MMstQuZN2mFRwzfukIdLDZclPCKkAM=
# =L9oL
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 28 Sep 2025 01:11:39 AM PDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu:
target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()
target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()
target/loongarch: Invalid tlb entry in invalidate_tlb()
target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid
target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g
target/loongarch: Change return value type with loongarch_tlb_search_cb()
target/loongarch: Add common API loongarch_tlb_search_cb()
target/loongarch: Add tlb search callback in loongarch_tlb_search()
target/loongarch: Fix page size set issue with CSR_STLBPS
target/loongarch: Update TLB index selection method
target/loongarch: Reduce TLB flush with helper_tlbwr
target/loongarch: Add parameter tlb pointer with fill_tlb_entry
target/loongarch: Use mmu idx bitmap method when flush TLB
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/d6dfd8d40ceb...4975b64efb5a
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