Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 58c497fac60dc9882b8456e042b6c5b6f0e3a811
https://github.com/qemu/qemu/commit/58c497fac60dc9882b8456e042b6c5b6f0e3a811
Author: Zejun Zhao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: Correct mmu-type property of sifive_u harts in device tree
Correct mmu-type property of sifive_u harts from Sv48 to Sv39 in 64-bit
mode since it's the only supported SATP mode.
Signed-off-by: Zejun Zhao <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 02dd56a295dffbef8fba1a0605936f5c1548b714
https://github.com/qemu/qemu/commit/02dd56a295dffbef8fba1a0605936f5c1548b714
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Explode MO_TExx -> MO_TE | MO_xx
Extract the implicit MO_TE definition in order to replace
it in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/hexagon); \
done
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a24defd419a1430b8ee5a34e8639a7d6e9441839
https://github.com/qemu/qemu/commit/a24defd419a1430b8ee5a34e8639a7d6e9441839
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_amo()
All callers of gen_amo() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b09e0f30e7a8b96c4abbbbe3d20ecef7f1c1f221
https://github.com/qemu/qemu/commit/b09e0f30e7a8b96c4abbbbe3d20ecef7f1c1f221
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_inc()
All callers of gen_inc() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4413ad413260e8983098dc254204456265ec82c3
https://github.com/qemu/qemu/commit/4413ad413260e8983098dc254204456265ec82c3
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_load() / gen_store()
All callers of gen_load() / gen_store() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c83da477801039b88d4efdee4be1ce32de44e47e
https://github.com/qemu/qemu/commit/c83da477801039b88d4efdee4be1ce32de44e47e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
All callers of gen_load_idx() / gen_store_idx() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 507e86947d41fd690d794b1c2b4e3597412546d1
https://github.com/qemu/qemu/commit/507e86947d41fd690d794b1c2b4e3597412546d1
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
All callers of gen_fload_idx() / gen_fstore_idx() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cdfe0ffd0d36f12cbe7b715b3165f796efb0302d
https://github.com/qemu/qemu/commit/cdfe0ffd0d36f12cbe7b715b3165f796efb0302d
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_storepair_tl()
All callers of gen_storepair_tl() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 7698b05c2824fce7301d6386c4f69319e6bcd1aa
https://github.com/qemu/qemu/commit/7698b05c2824fce7301d6386c4f69319e6bcd1aa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_cmpxchg*()
All callers of gen_cmpxchg() / gen_cmpxchg64() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c838cf671e355cc57929165616b04bc49e1b49e2
https://github.com/qemu/qemu/commit/c838cf671e355cc57929165616b04bc49e1b49e2
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
All callers of gen_lr() / gen_sc() set the MO_TE and MO_ALIGN flags.
Set them once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 20e865d47d1664e07e6aad98b9582920505d4656
https://github.com/qemu/qemu/commit/20e865d47d1664e07e6aad98b9582920505d4656
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
Log Message:
-----------
target/riscv: Factor MemOp variable out when MO_TE is set
In preparation of automatically replacing the MO_TE flag
in the next commit, use an local @memop variable.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 96bc1182ea1a51c5e797536b2f0fd42971da8a40
https://github.com/qemu/qemu/commit/96bc1182ea1a51c5e797536b2f0fd42971da8a40
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Introduce mo_endian() helper
mo_endian() returns the target endianness from DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: fa9a228acfc7d8f9a1fb0a5955c0bb2485d886b0
https://github.com/qemu/qemu/commit/fa9a228acfc7d8f9a1fb0a5955c0bb2485d886b0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Introduce mo_endian_env() helper
mo_endian_env() returns the target endianness from CPUArchState.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
[ Changes by AF:
- Only define mo_endian_env() for softmmu
]
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3dd1b6f12587162d92c3b7a56035aa95fc5c17b9
https://github.com/qemu/qemu/commit/3dd1b6f12587162d92c3b7a56035aa95fc5c17b9
Author: Guenter Roeck <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO
bus
The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses.
To be able to support two PHY instances on a single MDIO bus, two properties
are needed: First, there needs to be a flag indicating if the MDIO bus on
a given Ethernet interface is connected. If not, attempts to read from this
bus must always return 0xffff. Implement this property as phy-connected.
Second, if the MDIO bus on an interface is active, it needs a link to the
consumer interface to be able to provide PHY access for it. Implement this
property as phy-consumer.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 160d6f09bc368b2f14029dcc6c25021ce52cac33
https://github.com/qemu/qemu/commit/160d6f09bc368b2f14029dcc6c25021ce52cac33
Author: Guenter Roeck <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 71dd56e0ba3e67abed8e07f5da602b403cd590eb
https://github.com/qemu/qemu/commit/71dd56e0ba3e67abed8e07f5da602b403cd590eb
Author: Guenter Roeck <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
hw/net/cadence_gem: Add pcs-enabled property
The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel.
Add pcs-enabled property to to let the driver know if PCS should be
enabled. Set the flag to false by default (indicating that PCS is disabled)
to match the exiting code.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ecfec7df59a982f556fb756d21c3d6459cdbf06b
https://github.com/qemu/qemu/commit/ecfec7df59a982f556fb756d21c3d6459cdbf06b
Author: Guenter Roeck <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
microchip icicle: Enable PCS on Cadence Ethernet
PCS needs to be enabled for SGMII to be supported by the Linux kernel.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ecd8fa3e35734a22910f96b1e6c12e3148b57825
https://github.com/qemu/qemu/commit/ecd8fa3e35734a22910f96b1e6c12e3148b57825
Author: Jialong Yang <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
aplic: fix mask for smsiaddrcfgh
4.5.4. Supervisor MSI address configuration (smsiaddrcfg and
smsiaddrcfgh)
smsiaddrcfgh:
bits 22:20 LHXS(WARL)
bits 11:0 High Base PPN(WARL)
Signed-off-by: Jialong Yang <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: acf4aeb3a0a4fe9f0912604dc1ddd0fae2c34f45
https://github.com/qemu/qemu/commit/acf4aeb3a0a4fe9f0912604dc1ddd0fae2c34f45
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc: Allow gaps in hartids for aclint and aplic
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 562962128d535bd60b8b4a1a8712bd8e5d14accf
https://github.com/qemu/qemu/commit/562962128d535bd60b8b4a1a8712bd8e5d14accf
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add cpu_set_exception_base
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2f49deebab0960c4d42a268c6d2ab5ec3175ddea
https://github.com/qemu/qemu/commit/2f49deebab0960c4d42a268c6d2ab5ec3175ddea
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu_vendorid.h
Log Message:
-----------
target/riscv: Add MIPS P8700 CPU
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 60f8df281ee54d04de50dced4d6c7f9b55406958
https://github.com/qemu/qemu/commit/60f8df281ee54d04de50dced4d6c7f9b55406958
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/meson.build
A target/riscv/mips_csr.c
Log Message:
-----------
target/riscv: Add MIPS P8700 CSRs
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 34370b607ec9cfd1b7f63535fa3b82865e8e5c20
https://github.com/qemu/qemu/commit/34370b607ec9cfd1b7f63535fa3b82865e8e5c20
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
A target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
A target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add mips.ccmov instruction
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2585149396656e6738a2b622e15c85dcce1d1f13
https://github.com/qemu/qemu/commit/2585149396656e6738a2b622e15c85dcce1d1f13
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add mips.pref instruction
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5324ab70a6fde6730012166e5068014ea10a7d60
https://github.com/qemu/qemu/commit/5324ab70a6fde6730012166e5068014ea10a7d60
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add Xmipslsp instructions
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6994d6f900007eee8582255c4871ec1a1b5e6610
https://github.com/qemu/qemu/commit/6994d6f900007eee8582255c4871ec1a1b5e6610
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cmgcr.c
A include/hw/misc/riscv_cmgcr.h
Log Message:
-----------
hw/misc: Add RISC-V CMGCR device implementation
Add RISC-V implementation of the Coherent Manager Global Control
Register (CMGCR) device. It is based on the existing MIPS CMGCR
implementation but adapted for RISC-V systems.
The CMGCR device provides global system control for multi-core
configurations in RISC-V systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 141c399907befdc1d9607ad1685f99b06f67cc17
https://github.com/qemu/qemu/commit/141c399907befdc1d9607ad1685f99b06f67cc17
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cpc.c
A include/hw/misc/riscv_cpc.h
Log Message:
-----------
hw/misc: Add RISC-V CPC device implementation
Add RISC-V implementation of the Cluster Power Controller (CPC) device.
It is based on the existing MIPS CPC implementations but adapted for
RISC-V systems.
The CPC device manages power control for CPU clusters in RISC-V
systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 99b6fa41ad15006955a6cbbc385550662cc84b3f
https://github.com/qemu/qemu/commit/99b6fa41ad15006955a6cbbc385550662cc84b3f
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/misc/Kconfig
A hw/riscv/cps.c
M hw/riscv/meson.build
A include/hw/riscv/cps.h
Log Message:
-----------
hw/riscv: Add support for RISCV CPS
Add support for the Coherent Processing System for RISC-V.
This enables SMP support for RISC-V boards that require
cache-coherent multiprocessor systems.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 1d8d24dd5d7d8996605cf0ecbc082344e6079bc9
https://github.com/qemu/qemu/commit/1d8d24dd5d7d8996605cf0ecbc082344e6079bc9
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M configs/devices/riscv64-softmmu/default.mak
A docs/system/riscv/mips.rst
M docs/system/target-riscv.rst
M hw/riscv/Kconfig
A hw/riscv/boston-aia.c
M hw/riscv/meson.build
Log Message:
-----------
hw/riscv: Add support for MIPS Boston-aia board mode
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z.
Ex: Use 4 cores and 2 threads with each core to
have 8 smp cpus as follows.
qemu-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 602cfa0b03031e16906df546857184631a33c5da
https://github.com/qemu/qemu/commit/602cfa0b03031e16906df546857184631a33c5da
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/riscv/boston-aia.c
Log Message:
-----------
riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 1dc4c72f2919f0260b1b872aece9289a94fea9cd
https://github.com/qemu/qemu/commit/1dc4c72f2919f0260b1b872aece9289a94fea9cd
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M tests/functional/riscv64/meson.build
A tests/functional/riscv64/test_boston.py
Log Message:
-----------
test/functional: Add test for boston-aia board
Add functional test for Boston AIA board. The P8700 RISC-V based
CPU by MIPS supports it at the moment.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 95a97b4a38dfeb00b9c57571c8f740e70e781f7d
https://github.com/qemu/qemu/commit/95a97b4a38dfeb00b9c57571c8f740e70e781f7d
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: fix env->priv setting in reset_regs_csr()
This patch was originally made by Gitlab user Bo Gan (@ganboing) 4
months ago in the context of issue [1]. I asked the author to send a
patch to the mailing list ~3 months ago and got no reply. I'm sending
the patch myself because we already missed 10.1 without this fix.
I'll also just post verbatim Bo Gan comment in the commit msg:
"In RISCV Linux with KVM enabled, gdbstub is broken. The
get_physical_address isn't able to page-walk correctly and resolve the
physical page. This is due to that the vcpu is being treated as starting
in M mode even if KVM enabled. However, with KVM, the vcpu is actually
started in S mode. The mmu_idx will give 3 (M), instead of 1 (S),
resulting in Guest PA == VA (wrong)!"
Set env->priv to PRV_S in kvm_riscv_reset_regs_csr() since the VCPU is
always started in S-mode for KVM.
[1] https://gitlab.com/qemu-project/qemu/-/issues/2991
Cc: [email protected]
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2991
Originally-by: Bo Gan (@ganboing in Gitlab)
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 51e525dc4eee1f74198053f07a2808365605135f
https://github.com/qemu/qemu/commit/51e525dc4eee1f74198053f07a2808365605135f
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv/riscv-qmp-cmds.c: coverity-related fixes
Coverity CID 1641401 reports that, in reg_is_ulong_integer(), we're
dereferencing a NULL pointer in "reg1" when using it in strcasecmp()
call. A similar case is reported with CID 1641393.
In theory that will never happen - it's guaranteed that both "reg1" and
"reg2" is non-NULL because we're retrieving them in compile-time from
static arrays. Coverity doesn't know that though.
To make Coverity happier and add a bit more clarity in the code,
g_assert() each token to make it clear that those 2 values aren't
supposed to be NULL ever. Do that in both reg_is_ulong_integer() and
reg_is_u64_fpu().
We're also taking the opportunity to implement suggestions made by Peter
in [1] in both functions:
- use g_strsplit() instead of strtok();
- use g_ascii_strcasecmp() instead of strcasecmp().
[1]
https://lore.kernel.org/qemu-devel/cafeaca_y4bwd9ganbxnpty2mv80vg_jp+a-vkqs5v6f0+bf...@mail.gmail.com/
Coverity: CID 1641393, 1641401
Fixes: e06d209aa6 ("target/riscv: implement MonitorDef HMP API")
Suggested-by: Peter Maydell <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 346cbe97ec1adcb72d4a8b3662b8cdb41abee72b
https://github.com/qemu/qemu/commit/346cbe97ec1adcb72d4a8b3662b8cdb41abee72b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: fix riscv_cpu_sirq_pending() mask
We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode
pending interrupts without apparent reason. There's no special treatment
for these ints as far as the spec goes, and this filtering is causing
read_stopi() to miss those VS interrupts [1].
We shouldn't return delegated VS interrupts in S-mode though, so change
the current mask with "~env->hideleg". Note that this is the same
handling we're doing in riscv_cpu_mirq_pending() and env->mideleg.
[1] https://gitlab.com/qemu-project/qemu/-/issues/2820
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 6938cf7378c63bb8610c82b681789c2174c1e52e
https://github.com/qemu/qemu/commit/6938cf7378c63bb8610c82b681789c2174c1e52e
Author: Akihiko Odaki <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Fix a uninitialized variable warning
riscv_cpu_validate_v() left its variable, min_vlen, uninitialized if
no vector extension is available, causing a compiler warning.
Re-define riscv_cpu_validate_v() as no-op when no vector extension is
available to prevent the scenario that will read the unintialized
variable by construction. It also simplifies its caller as a bonus.
Signed-off-by: Akihiko Odaki <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0c999b666960121d521523ae251a96438c3121eb
https://github.com/qemu/qemu/commit/0c999b666960121d521523ae251a96438c3121eb
Author: Jay Chang <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg_fields.h.inc
Log Message:
-----------
target/riscv: Make PMP granularity configurable
Previously, the PMP granularity in qemu always used a minimum
granularity of 4 bytes, this patch add pmp-granularity to allow
platforms to configure the value.
A new CPU parameter pmp-granularity has been introduced to the QEMU
command line. For example:
-cpu rv64, g=true, c=true, pmp=true, pmp-granularity=1024
If no specific value is provided, the default value is 4 bytes.
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 741566c3e07fd34ed28d4464d1d7fda67db12925
https://github.com/qemu/qemu/commit/741566c3e07fd34ed28d4464d1d7fda67db12925
Author: Jay Chang <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Make PMP CSRs conform to WARL constraints
This patch ensure pmpcfg and pmpaddr comply with WARL constraints.
When the PMP granularity is greater than 4 bytes, NA4 mode is not valid
per the spec and will be silently ignored.
According to the spec, changing pmpcfg.A only affects the "read" value
of pmpaddr. When G > 2 and pmpcfg.A is NAPOT, bits pmpaddr[G-2:0] read
as all ones. When G > 1 and pmpcfg.A is OFF or TOR, bits pmpaddr[G-1:0]
read as all zeros. This allows software to read back the correct
granularity value.
In addition, when updating the PMP address rule in TOR mode,
the start and end addresses of the PMP region should be aligned
to the PMP granularity. (The current SPEC only state in TOR mode
that bits pmpaddr[G-1:0] do not affect the TOR address-matching logic.)
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a5f72ed1e10e12090588846d6897f2b9596de0f2
https://github.com/qemu/qemu/commit/a5f72ed1e10e12090588846d6897f2b9596de0f2
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M configs/devices/riscv64-softmmu/default.mak
A docs/system/riscv/mips.rst
M docs/system/target-riscv.rst
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cmgcr.c
A hw/misc/riscv_cpc.c
M hw/net/cadence_gem.c
M hw/riscv/Kconfig
A hw/riscv/boston-aia.c
A hw/riscv/cps.c
M hw/riscv/meson.build
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
A include/hw/misc/riscv_cmgcr.h
A include/hw/misc/riscv_cpc.h
M include/hw/net/cadence_gem.h
A include/hw/riscv/cps.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/cpu_helper.c
M target/riscv/cpu_vendorid.h
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
A target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/meson.build
A target/riscv/mips_csr.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/riscv-qmp-cmds.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
A target/riscv/xmips.decode
M tests/functional/riscv64/meson.build
A tests/functional/riscv64/test_boston.py
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20251023' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 10.2
* Correct mmu-type property of sifive_u harts in device tree
* Centralize MO_TE uses in a pair of helpers
* Fix Ethernet interface support for microchip-icicle-kit
* Fix mask for smsiaddrcfgh
* Add support for MIPS P8700 CPU
* Fix env->priv setting in reset_regs_csr()
* Coverity-related fixes
* Fix riscv_cpu_sirq_pending() mask
* Fix a uninitialized variable warning
* Make PMP granularity configurable
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# gpg: Signature made Wed 22 Oct 2025 11:12:54 PM CDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
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* tag 'pull-riscv-to-apply-20251023' of https://github.com/alistair23/qemu: (37
commits)
target/riscv: Make PMP CSRs conform to WARL constraints
target/riscv: Make PMP granularity configurable
target/riscv: Fix a uninitialized variable warning
target/riscv: fix riscv_cpu_sirq_pending() mask
target/riscv/riscv-qmp-cmds.c: coverity-related fixes
target/riscv/kvm: fix env->priv setting in reset_regs_csr()
test/functional: Add test for boston-aia board
riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
hw/riscv: Add support for MIPS Boston-aia board mode
hw/riscv: Add support for RISCV CPS
hw/misc: Add RISC-V CPC device implementation
hw/misc: Add RISC-V CMGCR device implementation
target/riscv: Add Xmipslsp instructions
target/riscv: Add mips.pref instruction
target/riscv: Add mips.ccmov instruction
target/riscv: Add MIPS P8700 CSRs
target/riscv: Add MIPS P8700 CPU
target/riscv: Add cpu_set_exception_base
hw/intc: Allow gaps in hartids for aclint and aplic
aplic: fix mask for smsiaddrcfgh
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/c0e80879c876...a5f72ed1e10e
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