Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b6478122f059274b19805e14d12f76d2c0272ad4
https://github.com/qemu/qemu/commit/b6478122f059274b19805e14d12f76d2c0272ad4
Author: GuoHan Zhao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/uefi/ovmf-log.c
Log Message:
-----------
hw/uefi/ovmf-log: Fix memory leak in hmp_info_firmware_log
The FirmwareLog object returned by qmp_query_firmware_log() was
not being freed, causing a memory leak.
Use g_autoptr to ensure the object is automatically freed when
it goes out of scope.
Fixes: c8aa8120313f ("hw/uefi: add 'info firmware-log' hmp monitor command.")
Signed-off-by: GuoHan Zhao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Gerd Hoffmann <[email protected]>
Commit: 6447334a31bc65cd3192ada3ac75a5f2fdeaa03b
https://github.com/qemu/qemu/commit/6447334a31bc65cd3192ada3ac75a5f2fdeaa03b
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Use auto method with PTW feature
PTW is short for page table walker, it is hardware page table walker
function. With PTW supported, hardware MMU will parse page table
table and update TLB entries automatically.
This patch adds type OnOffAuto for PTW feature setting.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 5cba5a518bf50d790deff0d6188d2ebd299bc3cc
https://github.com/qemu/qemu/commit/5cba5a518bf50d790deff0d6188d2ebd299bc3cc
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
Log Message:
-----------
target/loongarch: Add CSR_PWCH write helper function
Bit HPTW_EN in register CSR_PWCH controls enabling hardware page
table walker feature when PTW feature is enabled. Otherwise it is
reserved bit.
Here add register CSR_PWCH write helper function.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 7b7c6fae9bce5d1314f38b66dbf4bf25e862af3f
https://github.com/qemu/qemu/commit/7b7c6fae9bce5d1314f38b66dbf4bf25e862af3f
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add present and write bit with pte entry
With hardware PTW feature enabled, Present bit and Write bit is checked
by hardware, rather Valid bit and Dirty bit. Bit P means that the page is
valid and present, and bit W means that the page is writable.
The original V bit is treated as access bit, hardware sets this bit if
there is a read or write access. Bit D bit is updated by hardware if
there is a write access.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 261612da4eec561f0745d557345c013a78c109bd
https://github.com/qemu/qemu/commit/261612da4eec561f0745d557345c013a78c109bd
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-mmu.h
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add function sptw_prepare_tlb before adding tlb entry
With software page table walker, tlb entry comes from CSR registers.
however with hardware page table walker, tlb entry comes from page
table entry information directly, TLB CSR registers are not necessary.
Here add function sptw_prepare_context(), get tlb entry information
from TLB CSR registers.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: f19c905b92dbda4623a9e6874e63433564947b9a
https://github.com/qemu/qemu/commit/f19c905b92dbda4623a9e6874e63433564947b9a
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: target/loongarch: Add common function get_tlb_random_index()
With software PTW system, tlb index is calculated randomly when new
TLB entry is added. For hardware PTW, it is the same logic to add
new TLB entry.
Here common function get_tlb_random_index() is added to get random
tlb index when adding new TLB entry.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 117767df98d7607bfebf10676aab39d7ebc7280e
https://github.com/qemu/qemu/commit/117767df98d7607bfebf10676aab39d7ebc7280e
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add MMUContext parameter in fill_tlb_entry()
Function fill_tlb_entry() can be used with hardware PTW in future,
here add input parameter MMUContext in fill_tlb_entry().
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 72c29e7a917560b92da4e95b93aca53f73651487
https://github.com/qemu/qemu/commit/72c29e7a917560b92da4e95b93aca53f73651487
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu_helper.c
Log Message:
-----------
target/loongarch: Add debug parameter with loongarch_page_table_walker()
Add debug parameter with function loongarch_page_table_walker(),
in debug mode it is only to get physical address. And It used in
future HW PTW usage, bit dirty and access will be updated in HW
PTW mode.
Also function loongarch_page_table_walker() is renamed as
loongarch_ptw() for short.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 6c66c390f9d9d6f60eac13a98f2c31d84a36bc3a
https://github.com/qemu/qemu/commit/6c66c390f9d9d6f60eac13a98f2c31d84a36bc3a
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu_helper.c
Log Message:
-----------
target/loongarch: Reserve higher 48 bit PTE attribute with huge page
With PTE entry, high bit 48-63 is valid HW bit for PTE attribute,
for example bit 63 is RPLV and bit 62 is NX. With page directory table,
it is physical address of page table from view of HW, so high bit
48-63 need be discarded.
Here reverve high bit 48-63 with huge page since it is PTE entry, and
only discard it with page directory table.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 6f6925aa36611f966b1a58ae8eb03d2dd8197c64
https://github.com/qemu/qemu/commit/6f6925aa36611f966b1a58ae8eb03d2dd8197c64
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu_helper.c
Log Message:
-----------
target/loongarch: Move last PTE lookup into page table walker loop
The last PTE lookup sentence is much similiar with the whole page
table walker loop, move it into the whole loop.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 52c60ad5f0977951786b5a8b68835ed950016279
https://github.com/qemu/qemu/commit/52c60ad5f0977951786b5a8b68835ed950016279
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add field tlb_index to record TLB search info
With hardware PTW function, TLB entry will be searched at first.
If there is odd/even page on one TLB entry, and odd page is valid and
even page is none. When software access memory with address in even
page, hardware PTW will happen and fill new entry in the same TLB entry.
Here add field tlb_index to record TLB index when search TLB tables.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: d0472b89ba1664562081357692e6c51a09583a84
https://github.com/qemu/qemu/commit/d0472b89ba1664562081357692e6c51a09583a84
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add common interface update_tlb_index()
Common API update_tlb_index() is added here, it is to update TLB entry
with specified index. It is called by helper_tlbwr() now, also it can
be used by HW PTW when adding new TLB entry.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 1158eb13f128d021d76ed19c44799f293ce26126
https://github.com/qemu/qemu/commit/1158eb13f128d021d76ed19c44799f293ce26126
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add basic hardware PTW support
However with hardware PTW supported, hardware will search page table
with TLB miss. Also if there is no TLB miss however bit Present is not set,
hardware PTW will happen also. Because there is odd/even page in one TLB
entry on LoongArch system, for example in the first time odd TLB entry is
valid and even TLB entry is 0. When software accesses with address within
even page, there is no TLB miss only that TLB entry is 0. In this
condition, hardwre PTW will happen also.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 80470b73def1f6fb24a7bcd7d43fb9bf0844721f
https://github.com/qemu/qemu/commit/80470b73def1f6fb24a7bcd7d43fb9bf0844721f
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
Log Message:
-----------
target/loongarch: Update matched ptw bit A/D with PTW supported
With hardware PTE supported, bit A will be set if there is read access
or instruction fetch, and bit D will be set with write access.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 79ff2eee9a377f654ed0c3533a0874a0e7d6226d
https://github.com/qemu/qemu/commit/79ff2eee9a377f654ed0c3533a0874a0e7d6226d
Author: Bibo Mao <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add bit A/D checking in TLB entry with PTW supported
With read/write access, add bit A/D checking if hardware PTW is
supported. If no matched, hardware page table walk is called. And
then bit A/D is updated in PTE entry and TLB entry is updated also.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 11b4071503a2a70f21c03892edc73f8ad029e743
https://github.com/qemu/qemu/commit/11b4071503a2a70f21c03892edc73f8ad029e743
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-3.0
pseries-3.0 had been deprecated and due for removal now as per policy.
Also remove legacy irq support which existed for pre pseries-3.1 machines.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: d9b3b2079a2d7418b8f47e745326bfefc76b05bf
https://github.com/qemu/qemu/commit/d9b3b2079a2d7418b8f47e745326bfefc76b05bf
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr.h
Log Message:
-----------
hw/ppc/spapr: Remove SpaprMachineClass::nr_xirqs field
The SpaprMachineClass::nr_xirqs field was only used by the
pseries-3.0 machine, which got removed. Remove it as now unused.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: ca9c5112f640f85524d0a3cc16a44e96eb69fb38
https://github.com/qemu/qemu/commit/ca9c5112f640f85524d0a3cc16a44e96eb69fb38
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-3.1
pseries-3.1 had been deprecated and due for removal now as per policy.
Also remove backward compatibility flags and related code introduced for
pre pseries-4.0 machines.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 5c1e7eb37d5af317339ad8951ff4ac64ecdea302
https://github.com/qemu/qemu/commit/5c1e7eb37d5af317339ad8951ff4ac64ecdea302
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc/spapr: Inline spapr_dtb_needed()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 3d8939da6fcf191220e0668e778c4b98ff6d8316
https://github.com/qemu/qemu/commit/3d8939da6fcf191220e0668e778c4b98ff6d8316
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr_events.c
Log Message:
-----------
hw/ppc/spapr: Inline few SPAPR_IRQ_* uses
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: ca70ed2738da9d04e81c5f0d91430503e0eac6f4
https://github.com/qemu/qemu/commit/ca70ed2738da9d04e81c5f0d91430503e0eac6f4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc/kvm: Remove kvmppc_get_host_serial() as unused
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 994abe73f9f649c6bde19fbc997004f4c5ab9f6c
https://github.com/qemu/qemu/commit/994abe73f9f649c6bde19fbc997004f4c5ab9f6c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc/kvm: Remove kvmppc_get_host_model() as unused
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 07718fe66060111821ffd38f1eaffcaec307db79
https://github.com/qemu/qemu/commit/07718fe66060111821ffd38f1eaffcaec307db79
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-4.0
pseries-4.0 had been deprecated and due for removal now as per policy.
Also remove pre-4.1 migration hacks which were introduced for backward
compatibility.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
[PMD: Remove SpaprMachineClass::pre_4_1_migration field]
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: cc62474851cf45017e7be13315a7f2c4723be33f
https://github.com/qemu/qemu/commit/cc62474851cf45017e7be13315a7f2c4723be33f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
hw/ppc/spapr: Remove SpaprMachineClass::phb_placement callback
The SpaprMachineClass::phb_placement callback was only used by
the pseries-4.0 machine, which got removed. Remove it as now
unused, directly calling spapr_phb_placement().
Move spapr_phb_placement() definition to avoid forward declaration.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 3d8736467fc93325b9bd730fa933bbd9b602b2f3
https://github.com/qemu/qemu/commit/3d8736467fc93325b9bd730fa933bbd9b602b2f3
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-4.1
Remove the pseries-4.1 machine specific logic as had been deprecated and
due for removal now as per policy.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 448b5be6253fb17d90f61902a75806d917ad4f78
https://github.com/qemu/qemu/commit/448b5be6253fb17d90f61902a75806d917ad4f78
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: remove deprecated machine pseries-4.2
Remove the pseries-4.2 machine specific logic as had been deprecated and
due for removal now as per policy.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 32a027f9404aee9c9c57a41abcea5dde5bf5e518
https://github.com/qemu/qemu/commit/32a027f9404aee9c9c57a41abcea5dde5bf5e518
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/amigaone.c
Log Message:
-----------
ppc/amigaone: Free allocated struct
In create_bd_info function a bd_info struct is allocated but never
freed. Mark it g_autofree to avoid leaking it.
Fixes: 34f053d86b (ppc/amigaone: Add kernel and initrd support)
Resolves: Coverity CID 1641398
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: e09a4dd4dcbbbff4ed213e829db6e10786c6c617
https://github.com/qemu/qemu/commit/e09a4dd4dcbbbff4ed213e829db6e10786c6c617
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/vof.c
Log Message:
-----------
ppc/vof: Make nextprop behave more like Open Firmware
The FDT does not normally store name properties but reconstructs it
from path but Open Firmware specification says each node should at
least have this property. This is correctly handled in getprop but
nextprop should also return it even if not present as a property.
Explicit name properties are still allowed because they are needed
e.g. on the root node that guests expect to have specific names as
seen on real machines instead of being empty so sometimes the node
name may need to be overriden. For example on pegasos MorphOS checks
the name of "/" and expects to find bplan,Pegasos2 which is how it
identifies the machine.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Alexey Kardashevskiy <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/366f14ce852415cc079727c54ac21a2aa6ff3917.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 63a9cc05807cbdbc1dbea736b312d87538c6273c
https://github.com/qemu/qemu/commit/63a9cc05807cbdbc1dbea736b312d87538c6273c
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Remove explicit name properties from device tree
These are not needed any more now that VOF can handle it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/fa36ab5a04e10c6acb89583f646aad83df2b0b13.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 9099b430a46ac8f513ee91bb4076b3f482babee1
https://github.com/qemu/qemu/commit/9099b430a46ac8f513ee91bb4076b3f482babee1
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
M pc-bios/dtb/meson.build
A pc-bios/dtb/pegasos2.dtb
A pc-bios/dtb/pegasos2.dts
Log Message:
-----------
hw/ppc/pegasos2: Change device tree generation
We generate a flattened device tree programmatically for VOF. Change
this to load the static parts from a device tree blob and only
generate the parts that depend on run time conditions such as CPU
type, memory size and PCI devices. Moving the static parts in a dts
makes the board code simpler and more generic.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/383891fc2696609b27d2de9773efe1b4f493e333.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 4f5ba146af4f18c0261c74b204e9b9b8d2735070
https://github.com/qemu/qemu/commit/4f5ba146af4f18c0261c74b204e9b9b8d2735070
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Remove fdt pointer from machine state
The machine class has a field for storing the fdt so we don't need our
own and can use that instead.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/f4355b8d2889aba19d28001e61ac3f9937fc5250.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: ac93f74b281893e383c244b8a922e270fe7c830d
https://github.com/qemu/qemu/commit/ac93f74b281893e383c244b8a922e270fe7c830d
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Rename mv field in machine state
Use more generic name for the field used to store the north bridge in
the machine state.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/f1c189f16a260377abe0d270e778f2738649446a.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 25d86d4f29f9712f8602d5768895d210466eb05a
https://github.com/qemu/qemu/commit/25d86d4f29f9712f8602d5768895d210466eb05a
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Add south bridge pointer in the machine state
Add field for the south bridge in machine state to have both north and
south bridges in it.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/654d3223b418d5bb2ba08a2b014375c2abf341aa.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 4c17dcff41696a13c1ba50c789ea571b894b053f
https://github.com/qemu/qemu/commit/4c17dcff41696a13c1ba50c789ea571b894b053f
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Move PCI IRQ routing setup to a function
Collect steps of setting up PCI IRQ routing in one function.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/f5ff16a6933ab6e1f9e194d16ef85364ac3cf6df.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: d617218e1bcac10482a6392474079c1d4398adae
https://github.com/qemu/qemu/commit/d617218e1bcac10482a6392474079c1d4398adae
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Move hardware specific parts out of machine reset
Move the pegasos2 specific chipset reset out from machine reset to a
separate function and move generic parts that are not pegasos2
specific from build_fdt to machine reset so now build_fdt only
contains pegasos2 specific parts and can be renamed accordingly.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/f6633a68a72aad4fefb8d2373b52561f8ca8d41d.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 2c378545d02e0aa47c9234bf8c4028a9faaf72d1
https://github.com/qemu/qemu/commit/2c378545d02e0aa47c9234bf8c4028a9faaf72d1
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Introduce abstract superclass
Rename machine state struct to PegasosMachineState as it will be used
for pegasos1 too.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/a09590a5da4572c9d392542f5c3793e6eb08ab9e.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: a310dbfade83b52b31f898fa82395e08aa9ae189
https://github.com/qemu/qemu/commit/a310dbfade83b52b31f898fa82395e08aa9ae189
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Add bus frequency to machine state
Store the bus frequency in the machine state and set it from instance
init method.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/b69e21e353b7d7f22a34db5f13443f60f51c7238.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: d3a16439c370205e9d9fb2a002dc68fc17fab2be
https://github.com/qemu/qemu/commit/d3a16439c370205e9d9fb2a002dc68fc17fab2be
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Add Pegasos I emulation
The Pegasos II is a redesign of the original Pegasos (later marked I)
that replaces the north bridge and has updated firmware but otherwise
these are very similar. The Pegasos uses the same north bridge that
AmigaOne used which we already emulate so we can also easily emulate
Pegasos I.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/8f5bd07553b41d83a54f9df0bb93b76b22dea5c5.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 3c21f9dfcf8c8120e2fd5e8c5cbea61f21e7be69
https://github.com/qemu/qemu/commit/3c21f9dfcf8c8120e2fd5e8c5cbea61f21e7be69
Author: BALATON Zoltan <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M MAINTAINERS
M hw/ppc/pegasos2.c
M pc-bios/dtb/meson.build
A pc-bios/dtb/pegasos1.dtb
A pc-bios/dtb/pegasos1.dts
Log Message:
-----------
hw/ppc/pegasos2: Add VOF support for pegasos1
When running without firmware ROM using Virtual Open Firmware we need
to do some hardware initialisation and provide the device tree as the
machine firmware would normally do.
Signed-off-by: BALATON Zoltan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/d2d7f173dbd436b47382f384d5a93eb7e713424e.1761176219.git.bala...@eik.bme.hu
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: a728c87e966d4d4ca1675fbe7127c813fb8f66e1
https://github.com/qemu/qemu/commit/a728c87e966d4d4ca1675fbe7127c813fb8f66e1
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/spapr_fadump.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_fadump.h
Log Message:
-----------
hw/ppc: Implement fadump register command
Add skeleton to handle "ibm,configure-kernel-dump" rtas call in QEMU,
including register, unregister and invalidate commands.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
Verify basic details mandated by the PAPR, such as number of
inputs/output, and add handling for the three fadump commands:
regiser/unregister/invalidate.
The checks are based on the table in following requirement in PAPR v2.13:
"R1–7.3.30–1. For the Configure Platform Assisted Kernel Dump option ..."
Relevant section for the register command in PAPR is:
Section 7.3.30: "ibm,configure-kernel-dump RTAS call" (PAPR v2.13)
Note: Any modifications made by the kernel to the fadump memory
structure after the 'ibm,configure-kernel-dump' RTAS call returns will
not be reflected in QEMU, as QEMU retains the fadump memory structure
that was provided during fadump registration.
The kernel must unregister and re-register fadump to apply any changes
to the fadump memory structure.
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 03cb7661d2503780532fddc51f02c777774a3e4e
https://github.com/qemu/qemu/commit/03cb7661d2503780532fddc51f02c777774a3e4e
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr_fadump.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr_fadump.h
Log Message:
-----------
hw/ppc: Trigger Fadump boot if fadump is registered
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure registered through the
ibm,configure-kernel-dump call, the platform must process each
registered kernel dump section as required and, when available,
present the dump structure information to the operating system
through the “ibm,kernel-dump” property, updated with status for each
dump section, until the dump has been invalidated through the
ibm,configure-kernel-dump RTAS call.
If Fadump has been registered, trigger an Fadump boot (memory preserving
boot), if QEMU recieves a 'ibm,os-term' rtas call.
Implementing the fadump boot as:
* pause all vcpus (will need to save registers later)
* preserve memory regions specified by fadump (will be implemented
in future)
* do a memory preserving reboot (GUEST_RESET in QEMU doesn't clear
the memory)
Memory regions registered by fadump will be handled in a later patch.
Note: Preserving memory regions is not implemented yet so on an
"ibm,os-term" call will just trigger a reboot in QEMU if fadump is
registered, and the second kernel will boot as a normal boot (not
fadump boot)
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 6460c471768629adc4a915a998cafcfa30d6461a
https://github.com/qemu/qemu/commit/6460c471768629adc4a915a998cafcfa30d6461a
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr_fadump.c
M include/hw/ppc/spapr_fadump.h
Log Message:
-----------
hw/ppc: Preserve memory regions registered for fadump
While the first kernel boots, it registers memory regions for fadump
such as:
* CPU state data (has to be populated by the platform)
* HPTE state data (has to be populated by the platform)
* Real Mode Regions (platform should copy it to requested
destination addresses)
* OS defined regions (such as parameter save area)
Platform is also expected to modify the 'bytes_dumped' to the length of
data preserved/copied by platform (ideally same as the source length
passed by kernel).
The kernel passes source address and length for the memory regions, and
a destination address to where the memory is to be copied.
Implement the preserving/copying of the Real Mode Regions and the
Parameter Save Area in QEMU Pseries
The regions are copied in chunks instead of copying all at once.
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 7e69675d7fba1f00e8997fcd329445f60df51774
https://github.com/qemu/qemu/commit/7e69675d7fba1f00e8997fcd329445f60df51774
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr_fadump.c
M include/hw/ppc/spapr_fadump.h
Log Message:
-----------
hw/ppc: Implement saving CPU state in Fadump
Kernel expects CPU states/register states in the format mentioned in
"Register Save Area" in PAPR.
The platform (in our case, QEMU) saves each CPU register in the form of
an array of "register entries", the start and end of this array is
signified by "CPUSTRT" and "CPUEND" register entries respectively.
The CPUSTRT and CPUEND register entry also has 4-byte logical CPU ID,
thus storing the CPU ID corresponding to the array of register entries.
Each register, and CPUSTRT, CPUEND has a predefined identifier.
Implement calculating identifier for a given register in
'fadump_str_to_u64', which has been taken from the linux kernel
Similarly GPRs also have predefined identifiers, and a corresponding
64-bit resiter value (split into two 32-bit cells). Implement
calculation of GPR identifiers with 'fadump_gpr_id_to_u64'
PAPR has restrictions on particular order of few registers, and is
free to be in any order for other registers.
Some registers mentioned in PAPR have not been exported as they are not
implemented in QEMU / don't make sense in QEMU.
Implement saving of CPU state according to the PAPR document
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: dd29ab88a3441e70ccd8c410fa85561b8cc54861
https://github.com/qemu/qemu/commit/dd29ab88a3441e70ccd8c410fa85561b8cc54861
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_fadump.c
Log Message:
-----------
hw/ppc: Pass dump-sizes property for fadump in device tree
Platform (ie. QEMU) is expected to pass few device tree properties for
details for fadump:
* "ibm,configure-kernel-dump-sizes": Space required to store dump data
for firmware provided dump sections (ie. CPU & HPTE regions)
* "ibm,configure-kernel-dump-version": Versions of fadump supported
Pass the above device tree nodes so that kernel can reserve sufficient
space for preserving the CPU state data
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 041ed0e9ba29113cdccc608218f658502556e19c
https://github.com/qemu/qemu/commit/041ed0e9ba29113cdccc608218f658502556e19c
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc: Enable fadump for PSeries
With all support in place for preserving memory regions, enable fadump by
exporting the "ibm,kernel-dump" property in the device tree, representing
the fadump dump information, in case of a crash.
Currently "ibm,configure-kernel-dump" RTAS call is already registered,
which tells the kernel that the platform (QEMU) supports fadump.
Now, in case of a crash, if fadump was registered, we also pass
"ibm,kernel-dump" in device tree, which tells the kernel that the fadump
dump is active.
Pass "fadump=on" to enable Linux to use firmware assisted dump.
Logs of a linux boot with firmware assisted dump:
$ ./build/qemu-system-ppc64 -M pseries,x-vof=on --cpu power10 --smp 4 -m 4G
-kernel some-vmlinux -initrd some-initrd -append "debug fadump=on
crashkernel=1G" -nographic
[ 0.000000] fadump: Reserved 1024MB of memory at 0x00000040000000
(System RAM: 4096MB)
[ 0.000000] fadump: Initialized 0x40000000 bytes cma area at 1024MB from
0x400102a8 bytes of memory reserved for firmware-assisted dump
...
[ 1.084686] rtas fadump: Registration is successful!
...
# cat /sys/kernel/debug/powerpc/fadump_region
CPU :[0x00000040000000-0x000000400013df] 0x13e0 bytes, Dumped: 0x0
HPTE:[0x000000400013e0-0x000000400013df] 0x0 bytes, Dumped: 0x0
DUMP: Src: 0x00000000000000, Dest: 0x00000040010000, Size: 0x40000000,
Dumped: 0x0 bytes
[0x0000000921a000-0x0000000921a7ff]: cmdline append: ''
# echo c > /proc/sysrq-trigger
The fadump boot after crash:
[ 0.000000] rtas fadump: Firmware-assisted dump is active.
[ 0.000000] fadump: Updated cmdline: debug fadump=on crashkernel=1G
[ 0.000000] fadump: Firmware-assisted dump is active.
[ 0.000000] fadump: Reserving 3072MB of memory at 0x00000040000000 for
preserving crash data
....
# file /proc/vmcore
/proc/vmcore: ELF 64-bit LSB core file, 64-bit PowerPC or cisco 7500,
OpenPOWER ELF V2 ABI, version 1 (SYSV), SVR4-style
Analysing the vmcore with crash-utility:
KERNEL: vmlinux-6.14-rc2
DUMPFILE: vmcore-fc92fb373aa0
CPUS: 4
DATE: Wed Mar 12 23:39:23 CDT 2025
UPTIME: 00:00:22
LOAD AVERAGE: 0.13, 0.03, 0.01
TASKS: 95
NODENAME: buildroot
RELEASE: 6.12.0-rc4+
VERSION: #1 SMP Fri Jan 3 00:15:17 IST 2025
MACHINE: ppc64le (1000 Mhz)
MEMORY: 4 GB
PANIC: "Kernel panic - not syncing: sysrq triggered crash"
PID: 269
COMMAND: "sh"
TASK: c00000000a050b00 [THREAD_INFO: c00000000a050b00]
CPU: 0
STATE: TASK_RUNNING (PANIC)
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 945fd61c065a72712c78422e4fcffeb682714944
https://github.com/qemu/qemu/commit/945fd61c065a72712c78422e4fcffeb682714944
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M tests/functional/ppc64/meson.build
A tests/functional/ppc64/test_fadump.py
M tests/functional/qemu_test/linuxkernel.py
Log Message:
-----------
tests/functional: Add test for fadump in PSeries
Add testcases for testing fadump with PSeries and PSeries+KVM
combinations
It tests if fadump is successfully detected and registered in the first
kernel boot. Then crashes the kernel, and verifies whether we have a
/proc/vmcore in the 2nd boot
Also introduce 'wait_for_regex_console_pattern' to check for cases where
there is a single success message, but can have multiple failure
messages.
This is particularly useful for cases such as fadump, where the
success message is
"Reserved 1024MB ... successfully"
But at the same point, it can fail with multiple errors such as
"Not supported" or "Allocation failed"
'wait_for_regex_console_pattern' also has a timeout, for cases when we
know the success/failure should appear in a short amount of time,
instead of waiting for the much longer test timeout, such as kernels
with support of fadump will print the success/failure in earlyboot of
the kernel, while kernel without support of fadump won't print anything
for long time, and without a timeout the testcase keeps waiting till
longer test timeout
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 3db841bf1194b2720a08df2ee0a6ca517091ad0e
https://github.com/qemu/qemu/commit/3db841bf1194b2720a08df2ee0a6ca517091ad0e
Author: Aditya Gupta <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add entry for FADump (pSeries)
Add maintainer and reviewer for fadump subsystem.
Signed-off-by: Aditya Gupta <[email protected]>
Acked-by: Sourabh Jain <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: fe7d70872b2f9f834e2ae76989a59dff0f40a521
https://github.com/qemu/qemu/commit/fe7d70872b2f9f834e2ae76989a59dff0f40a521
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/intc/arm_gicv3_dist.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0
The GIC distributor registers GICD_TYPER2 is present when the
GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation
is only GICv4.0, so this register is RES0. However, since it's
reasonable for GICv4.1-aware software to read the register, expecting
the zero for GICv3 and GICv4.0, implement the case to avoid it being
logged as an invalid guest read.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 7ade034e66ce71d66090aca9695e10041bb0d646
https://github.com/qemu/qemu/commit/7ade034e66ce71d66090aca9695e10041bb0d646
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm: Drop DPRINTF macro
We don't generally like DPRINTF debug macros, preferring tracepoints.
In this case the macro is used in only three places (reset, realize,
and in the unlikely event the host kernel doesn't have GICv3 register
access support). These don't seem worth converting to tracepoints,
so simply delete the macro and its uses.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 97de03a0bf6ee07df4cfc910c1d709449f71ca47
https://github.com/qemu/qemu/commit/97de03a0bf6ee07df4cfc910c1d709449f71ca47
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/cpu-features.h
Log Message:
-----------
target/arm: Add isar feature test for FEAT_AIE
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f50cbc6e6c0293010505f0231d94eead8ade5878
https://github.com/qemu/qemu/commit/f50cbc6e6c0293010505f0231d94eead8ade5878
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement MAIR2_ELx and AMAIR2_ELx
Enable the SCR.AIEn bit in scr_write, and test it in aien_access.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3bbdeedd6a3444100d739d052d9740695956f8fe
https://github.com/qemu/qemu/commit/3bbdeedd6a3444100d739d052d9740695956f8fe
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Add AIE to ARMVAParameters
Allow the bit to be set in TCR2;
extract the bit in aa64_va_parameters.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 56ff19a5c26d7254619684e14c5fe1b773a46b68
https://github.com/qemu/qemu/commit/56ff19a5c26d7254619684e14c5fe1b773a46b68
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Drop trivial assert vs attrindx
We just extracted 3 bits; the <= 7 test is trivially true.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f6e40ee151e68fbd403925341185e9b038f19164
https://github.com/qemu/qemu/commit/f6e40ee151e68fbd403925341185e9b038f19164
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Use el local indexing mair_el
We already have regime_el() computed to a local.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7eaee7f73e798438a9630c502da19e61f1bfe34e
https://github.com/qemu/qemu/commit/7eaee7f73e798438a9630c502da19e61f1bfe34e
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Honor param.aie in get_phys_addr_lpae
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2132c93fb97db6fc52f29ba685f109d8db5b6f92
https://github.com/qemu/qemu/commit/2132c93fb97db6fc52f29ba685f109d8db5b6f92
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_AIE for -cpu max
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3f462d79a080060e54e39d31ce10fdf1a20317ef
https://github.com/qemu/qemu/commit/3f462d79a080060e54e39d31ce10fdf1a20317ef
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix reads of CNTFRQ_EL0 in linux-user mode
In commit bd8e9ddf6f6 ("target/arm: Refactor default generic timer
frequency handling") we changed how we initialized the generic timer
frequency as reported in the CNTFRQ_EL0 register. As part of that,
we chanegd the linux-user version of the CNTFRQ_EL0 sysreg from
having a constant value set at compile time through the .resetvalue
field to having a reset value which we compute in a .resetfn.
This accidentally broke the reading of CNTFRQ_EL0 in linux-user mode,
because the cpreg is marked as ARM_CP_CONST, which means we translate
it as a read of the compile-time constant value in the .resetvalue
field. This is now zero, so userspace sees a 0 frequency value.
Fix the bug by dropping the ARM_CP_CONST marking. This will cause us
to translate the read as a load of the value from the CPU state
struct cp15.c14_cntfrq field, which is where the real frequency value
now lives.
Cc: [email protected]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3159
Fixes: bd8e9ddf6f6 ("target/arm: Refactor default generic timer frequency
handling")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 59ad421d66df9e53b944475378b6fe389a61612d
https://github.com/qemu/qemu/commit/59ad421d66df9e53b944475378b6fe389a61612d
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset
Currently in arm_gicv3_icc_reset() we read the kernel's value of
ICC_CTLR_EL1 as part of resetting the CPU interface. This mostly
works, but we're actually breaking an assumption the kernel makes
that userspace only accesses the in-kernel GIC data when the VM is
totally paused, which may not be the case if a single vCPU is being
reset. The effect is that it's possible that the read attempt
returns EBUSY.
Avoid this by reading the kernel's value of the reset ICC_CTLR_EL1
once in device realize. This brings ICC_CTLR_EL1 into line with
the other cpuif registers, where we assume we know what the kernel
is resetting them to and just update QEMU's data structures in
arm_gicv3_icc_reset().
Reviewed-by: Salil Mehta <[email protected]>
Tested-by: Salil Mehta <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Commit: 0af7ba53fe126f653602f3abf1e37489e114867f
https://github.com/qemu/qemu/commit/0af7ba53fe126f653602f3abf1e37489e114867f
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Claim the Arm XML in gdb-xml
Add F: entries to the Arm CPU section to claim the Arm related
XML files in gdb-xml.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 841bb7d96f72efc4d825b7333b02bda32f3d04f7
https://github.com/qemu/qemu/commit/841bb7d96f72efc4d825b7333b02bda32f3d04f7
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M configs/targets/aarch64-bsd-user.mak
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64-softmmu.mak
M configs/targets/aarch64_be-linux-user.mak
A gdb-xml/aarch64-sme2.xml
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Implement SME2 support in gdbstub
For SME2, we need to expose the new ZT0 register in the gdbstub XML.
gdb documents that the requirements are:
> The ‘org.gnu.gdb.aarch64.sme2’ feature is optional. If present,
> then the ‘org.gnu.gdb.aarch64.sme’ feature must also be present.
> The ‘org.gnu.gdb.aarch64.sme2’ feature should contain the
> following:
>
> - ZT0 is a register of 512 bits (64 bytes). It is defined as a
> vector of bytes.
Implement this.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 7fd82461ddd41a27dfbbe83647810acaf6331ccc
https://github.com/qemu/qemu/commit/7fd82461ddd41a27dfbbe83647810acaf6331ccc
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub
GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls,
which will contain either just "tpidr", or else "tpidr" and "tpidr2".
This will be important for SME in future, because the lazy state
restoration scheme requires GDB to use the TPIDR2 information.
GDB doesn't currently implement that, but we should provide the
register via the XML so that we are ready when future GDB versions
support it.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: caa0e960979eada7518eeadc3757a0d2fb9765f6
https://github.com/qemu/qemu/commit/caa0e960979eada7518eeadc3757a0d2fb9765f6
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gdbstub/test-sme2.py
Log Message:
-----------
tests/tcg/aarch64: Add test case for SME2 gdbstub registers
Test the SME2 register exposure over gdbstub, in the same way
we already do for SME.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 33eff5c84d52e7186e0882ea5ee9ac5501c3deea
https://github.com/qemu/qemu/commit/33eff5c84d52e7186e0882ea5ee9ac5501c3deea
Author: Peter Maydell <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/net/rocker/rocker_of_dpa.c
Log Message:
-----------
hw/net/rocker: Don't overflow in of_dpa_mask2prefix()
In of_dpa_mask2prefix() we do "(2 << i)" for a loop where i can go up
to 31. At i == 31 we shift off the top end of an integer. This
doesn't actually calculate the wrong value in practice, because we
calculate 0 - 1 which is the 0xffffffff mask we wanted (and for QEMU
shifting off the top of a signed integer is not UB); but it makes
Coverity complain.
We could fix this simply by using "2ULL" (where the "(2ULL << i) - 1"
expression also evaluates to 0xffffffff for i == 31), but in fact
this function is a slow looping implementation of counting the number
of trailing zeroes in the (network-order) input mask:
0bxxxxxxxxx1 => 32
0bxxxxxxxx10 => 31
0bxxxxxxx100 => 30
...
0bx100000000 => 2
0b1000000000 => 1
0b0000000000 => 0
Replace the implementation with 32 - ctz32().
Coverity: CID 1547602
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 31a42bb0a30fc1887d70b08c254cff46033e9f63
https://github.com/qemu/qemu/commit/31a42bb0a30fc1887d70b08c254cff46033e9f63
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M target/loongarch/cpu-csr.h
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/cpu_helper.c
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20251023' of https://github.com/bibo-mao/qemu into
staging
loongarch queue
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# gpg: Signature made Thu 23 Oct 2025 06:44:36 AM CDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
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* tag 'pull-loongarch-20251023' of https://github.com/bibo-mao/qemu:
target/loongarch: Add bit A/D checking in TLB entry with PTW supported
target/loongarch: Update matched ptw bit A/D with PTW supported
target/loongarch: Add basic hardware PTW support
target/loongarch: Add common interface update_tlb_index()
target/loongarch: Add field tlb_index to record TLB search info
target/loongarch: Move last PTE lookup into page table walker loop
target/loongarch: Reserve higher 48 bit PTE attribute with huge page
target/loongarch: Add debug parameter with loongarch_page_table_walker()
target/loongarch: Add MMUContext parameter in fill_tlb_entry()
target/loongarch: target/loongarch: Add common function get_tlb_random_index()
target/loongarch: Add function sptw_prepare_tlb before adding tlb entry
target/loongarch: Add present and write bit with pte entry
target/loongarch: Add CSR_PWCH write helper function
target/loongarch: Use auto method with PTW feature
Signed-off-by: Richard Henderson <[email protected]>
Commit: d2cc2b1dfc35dc32a8ee2e12754c9afc10fc20b4
https://github.com/qemu/qemu/commit/d2cc2b1dfc35dc32a8ee2e12754c9afc10fc20b4
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M MAINTAINERS
M hw/ppc/amigaone.c
M hw/ppc/meson.build
M hw/ppc/pegasos2.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_events.c
A hw/ppc/spapr_fadump.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_vio.c
M hw/ppc/vof.c
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_fadump.h
M include/hw/ppc/spapr_irq.h
M pc-bios/dtb/meson.build
A pc-bios/dtb/pegasos1.dtb
A pc-bios/dtb/pegasos1.dts
A pc-bios/dtb/pegasos2.dtb
A pc-bios/dtb/pegasos2.dts
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M tests/functional/ppc64/meson.build
A tests/functional/ppc64/test_fadump.py
M tests/functional/qemu_test/linuxkernel.py
Log Message:
-----------
Merge tag 'pull-ppc-for-10.2-d2-20251023-1' of
https://gitlab.com/harshpb/qemu into staging
ppc queue for 10.2
* FADUMP Support for pSeries
* Pegasos II cleanup and Pegasos I emulation
* Deprecation of pseries 3.0 up till 4.2
* Coverity fix for amigaone (CID: 1641398)
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# gpg: Signature made Thu 23 Oct 2025 07:11:26 AM CDT
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# gpg: Good signature from "Harsh Prateek Bora <[email protected]>"
[undefined]
# gpg: aka "Harsh Prateek Bora <[email protected]>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-10.2-d2-20251023-1' of https://gitlab.com/harshpb/qemu: (32
commits)
MAINTAINERS: Add entry for FADump (pSeries)
tests/functional: Add test for fadump in PSeries
hw/ppc: Enable fadump for PSeries
hw/ppc: Pass dump-sizes property for fadump in device tree
hw/ppc: Implement saving CPU state in Fadump
hw/ppc: Preserve memory regions registered for fadump
hw/ppc: Trigger Fadump boot if fadump is registered
hw/ppc: Implement fadump register command
hw/ppc/pegasos2: Add VOF support for pegasos1
hw/ppc/pegasos2: Add Pegasos I emulation
hw/ppc/pegasos2: Add bus frequency to machine state
hw/ppc/pegasos2: Introduce abstract superclass
hw/ppc/pegasos2: Move hardware specific parts out of machine reset
hw/ppc/pegasos2: Move PCI IRQ routing setup to a function
hw/ppc/pegasos2: Add south bridge pointer in the machine state
hw/ppc/pegasos2: Rename mv field in machine state
hw/ppc/pegasos2: Remove fdt pointer from machine state
hw/ppc/pegasos2: Change device tree generation
hw/ppc/pegasos2: Remove explicit name properties from device tree
ppc/vof: Make nextprop behave more like Open Firmware
...
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0c34af48058150a3186c369a7173a0ff93e448d8
https://github.com/qemu/qemu/commit/0c34af48058150a3186c369a7173a0ff93e448d8
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M hw/uefi/ovmf-log.c
Log Message:
-----------
Merge tag 'uefi-20251023--pull-request' of https://gitlab.com/kraxel/qemu
into staging
hw/uefi: fix memory leak
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# 1YUyzcXIaJfxB+PGVNATx63oMFq88UdftxGNHonFMs0ARooOA9I=
# =BlTx
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 23 Oct 2025 08:28:02 AM CDT
# gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <[email protected]>" [unknown]
# gpg: aka "Gerd Hoffmann <[email protected]>" [unknown]
# gpg: aka "Gerd Hoffmann (private) <[email protected]>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* tag 'uefi-20251023--pull-request' of https://gitlab.com/kraxel/qemu:
hw/uefi/ovmf-log: Fix memory leak in hmp_info_firmware_log
Signed-off-by: Richard Henderson <[email protected]>
Commit: 88b1716a407459c8189473e4667653cb8e4c3df7
https://github.com/qemu/qemu/commit/88b1716a407459c8189473e4667653cb8e4c3df7
Author: Richard Henderson <[email protected]>
Date: 2025-10-23 (Thu, 23 Oct 2025)
Changed paths:
M MAINTAINERS
M configs/targets/aarch64-bsd-user.mak
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64-softmmu.mak
M configs/targets/aarch64_be-linux-user.mak
M docs/system/arm/emulation.rst
A gdb-xml/aarch64-sme2.xml
M hw/intc/arm_gicv3_dist.c
M hw/intc/arm_gicv3_kvm.c
M hw/intc/gicv3_internal.h
M hw/net/rocker/rocker_of_dpa.c
M include/hw/intc/arm_gicv3_common.h
M target/arm/cpregs.h
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/cpu64.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gdbstub/test-sme2.py
Log Message:
-----------
Merge tag 'pull-target-arm-20251023' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* target/arm: Enable FEAT_AIE for -cpu max
* target/arm: Fix reads of CNTFRQ_EL0 in linux-user mode
* target/arm: Implement SME2 support in gdbstub
* hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0
* hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset
* MAINTAINERS: Claim the Arm XML in gdb-xml
* hw/net/rocker: Don't overflow in of_dpa_mask2prefix()
# -----BEGIN PGP SIGNATURE-----
#
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# jiqlVqJfnTcsggfy2/nmY/zgdQDruNhvg8OrY1XM8Zhw7TT+1WFoh2K0OtgnxFi8
# pPpg15MMI872lMbn9U81qHFxfC82LXr4nw8hn6ox36FUSCDdqqdSjIkCb7OstyC9
# lrgd9WbmkeG9fJqhiSaKywgfvOGbfIfrRiJpKkSSeJQIjX8HxqjDCtOARvGw0duq
# 5no0CUpaUoPT6LFsl7/3wA==
# =ZRVN
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 23 Oct 2025 09:54:23 AM CDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>"
[unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20251023' of https://gitlab.com/pm215/qemu:
hw/net/rocker: Don't overflow in of_dpa_mask2prefix()
tests/tcg/aarch64: Add test case for SME2 gdbstub registers
target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub
target/arm: Implement SME2 support in gdbstub
MAINTAINERS: Claim the Arm XML in gdb-xml
hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset
target/arm: Fix reads of CNTFRQ_EL0 in linux-user mode
target/arm: Enable FEAT_AIE for -cpu max
target/arm: Honor param.aie in get_phys_addr_lpae
target/arm: Use el local indexing mair_el
target/arm: Drop trivial assert vs attrindx
target/arm: Add AIE to ARMVAParameters
target/arm: Implement MAIR2_ELx and AMAIR2_ELx
target/arm: Add isar feature test for FEAT_AIE
hw/intc/arm_gicv3_kvm: Drop DPRINTF macro
hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/c0e80879c876...88b1716a4074
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