Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: e41139eaad1d6ea7c52b8ebb5def2dcb84ff57e1
https://github.com/qemu/qemu/commit/e41139eaad1d6ea7c52b8ebb5def2dcb84ff57e1
Author: Zejun Zhao <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: Correct mmu-type property of sifive_u harts in device tree
Correct mmu-type property of sifive_u harts from Sv48 to Sv39 in 64-bit
mode since it's the only supported SATP mode.
Signed-off-by: Zejun Zhao <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 73ae67fd4e655021290abf7ccffd622e6e23ebab
https://github.com/qemu/qemu/commit/73ae67fd4e655021290abf7ccffd622e6e23ebab
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Explode MO_TExx -> MO_TE | MO_xx
Extract the implicit MO_TE definition in order to replace
it in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/hexagon); \
done
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cb2725db0cc314242dd8315823c90057e1b4e1ef
https://github.com/qemu/qemu/commit/cb2725db0cc314242dd8315823c90057e1b4e1ef
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_amo()
All callers of gen_amo() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 133080735cf2e7b0aabdf164d766690b65eb5418
https://github.com/qemu/qemu/commit/133080735cf2e7b0aabdf164d766690b65eb5418
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_inc()
All callers of gen_inc() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5ed09d6f7bf497f49d7ccfdfa664095dafa72c30
https://github.com/qemu/qemu/commit/5ed09d6f7bf497f49d7ccfdfa664095dafa72c30
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_load() / gen_store()
All callers of gen_load() / gen_store() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 23a56ce74ba6d00362693a3aba7fe4f76a720698
https://github.com/qemu/qemu/commit/23a56ce74ba6d00362693a3aba7fe4f76a720698
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
All callers of gen_load_idx() / gen_store_idx() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d46fa71ea99c4efd2e7fad0aa5c6efad15bc982b
https://github.com/qemu/qemu/commit/d46fa71ea99c4efd2e7fad0aa5c6efad15bc982b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
All callers of gen_fload_idx() / gen_fstore_idx() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6a58a38655fb242051e4b7c29aebe0fecbea37b4
https://github.com/qemu/qemu/commit/6a58a38655fb242051e4b7c29aebe0fecbea37b4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_storepair_tl()
All callers of gen_storepair_tl() set the MO_TE flag. Set it once in
the callee.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 9f14d9d98dc32fb8fe99ba5ae57a2fec3912d544
https://github.com/qemu/qemu/commit/9f14d9d98dc32fb8fe99ba5ae57a2fec3912d544
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Conceal MO_TE within gen_cmpxchg*()
All callers of gen_cmpxchg() / gen_cmpxchg64() set the MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c62bcc0048746c5dbfbf8cf390dafc473be31139
https://github.com/qemu/qemu/commit/c62bcc0048746c5dbfbf8cf390dafc473be31139
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
Log Message:
-----------
target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
All callers of gen_lr() / gen_sc() set the MO_TE and MO_ALIGN flags.
Set them once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6f825fd4911f61d198e11457eab9f707a925f34f
https://github.com/qemu/qemu/commit/6f825fd4911f61d198e11457eab9f707a925f34f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
Log Message:
-----------
target/riscv: Factor MemOp variable out when MO_TE is set
In preparation of automatically replacing the MO_TE flag
in the next commit, use an local @memop variable.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 504f7f304ff6a05da44571103832315910531d37
https://github.com/qemu/qemu/commit/504f7f304ff6a05da44571103832315910531d37
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Introduce mo_endian() helper
mo_endian() returns the target endianness from DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d652720ecc6e6b62d358db07fb1b1b4c2578243b
https://github.com/qemu/qemu/commit/d652720ecc6e6b62d358db07fb1b1b4c2578243b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Introduce mo_endian_env() helper
mo_endian_env() returns the target endianness from CPUArchState.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
[ Changes by AF:
- Only define mo_endian_env() for softmmu
]
Signed-off-by: Alistair Francis <[email protected]>
Commit: e530e5d034daf6865239b94705dd57c8c45cf4e4
https://github.com/qemu/qemu/commit/e530e5d034daf6865239b94705dd57c8c45cf4e4
Author: Guenter Roeck <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO
bus
The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses.
To be able to support two PHY instances on a single MDIO bus, two properties
are needed: First, there needs to be a flag indicating if the MDIO bus on
a given Ethernet interface is connected. If not, attempts to read from this
bus must always return 0xffff. Implement this property as phy-connected.
Second, if the MDIO bus on an interface is active, it needs a link to the
consumer interface to be able to provide PHY access for it. Implement this
property as phy-consumer.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a79a4b9c2e5fa276d7a3317e0fdfe42edbb04555
https://github.com/qemu/qemu/commit/a79a4b9c2e5fa276d7a3317e0fdfe42edbb04555
Author: Guenter Roeck <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 35a5e8792046df64df10550cd7de4bbc0a2c1018
https://github.com/qemu/qemu/commit/35a5e8792046df64df10550cd7de4bbc0a2c1018
Author: Guenter Roeck <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
hw/net/cadence_gem: Add pcs-enabled property
The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel.
Add pcs-enabled property to to let the driver know if PCS should be
enabled. Set the flag to false by default (indicating that PCS is disabled)
to match the exiting code.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cdbb7c3fa6f67d3370965cb0e4bbfdbca04c0913
https://github.com/qemu/qemu/commit/cdbb7c3fa6f67d3370965cb0e4bbfdbca04c0913
Author: Guenter Roeck <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
microchip icicle: Enable PCS on Cadence Ethernet
PCS needs to be enabled for SGMII to be supported by the Linux kernel.
Signed-off-by: Guenter Roeck <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5e3e066e4ac894aff3e8dd3a072bca9c1986b2ff
https://github.com/qemu/qemu/commit/5e3e066e4ac894aff3e8dd3a072bca9c1986b2ff
Author: Jialong Yang <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
aplic: fix mask for smsiaddrcfgh
4.5.4. Supervisor MSI address configuration (smsiaddrcfg and
smsiaddrcfgh)
smsiaddrcfgh:
bits 22:20 LHXS(WARL)
bits 11:0 High Base PPN(WARL)
Signed-off-by: Jialong Yang <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 49c24c2ae5c02ea5351f2657217befd272e5333c
https://github.com/qemu/qemu/commit/49c24c2ae5c02ea5351f2657217befd272e5333c
Author: Djordje Todorovic <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc: Allow gaps in hartids for aclint and aplic
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2a21cbee47a124edf43fc9ee156d7093e2f957fd
https://github.com/qemu/qemu/commit/2a21cbee47a124edf43fc9ee156d7093e2f957fd
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: fix env->priv setting in reset_regs_csr()
This patch was originally made by Gitlab user Bo Gan (@ganboing) 4
months ago in the context of issue [1]. I asked the author to send a
patch to the mailing list ~3 months ago and got no reply. I'm sending
the patch myself because we already missed 10.1 without this fix.
I'll also just post verbatim Bo Gan comment in the commit msg:
"In RISCV Linux with KVM enabled, gdbstub is broken. The
get_physical_address isn't able to page-walk correctly and resolve the
physical page. This is due to that the vcpu is being treated as starting
in M mode even if KVM enabled. However, with KVM, the vcpu is actually
started in S mode. The mmu_idx will give 3 (M), instead of 1 (S),
resulting in Guest PA == VA (wrong)!"
Set env->priv to PRV_S in kvm_riscv_reset_regs_csr() since the VCPU is
always started in S-mode for KVM.
[1] https://gitlab.com/qemu-project/qemu/-/issues/2991
Cc: [email protected]
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2991
Originally-by: Bo Gan (@ganboing in Gitlab)
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f131f10b63fac3bfa8f96c67a446c36bfcccbe6a
https://github.com/qemu/qemu/commit/f131f10b63fac3bfa8f96c67a446c36bfcccbe6a
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv/riscv-qmp-cmds.c: coverity-related fixes
Coverity CID 1641401 reports that, in reg_is_ulong_integer(), we're
dereferencing a NULL pointer in "reg1" when using it in strcasecmp()
call. A similar case is reported with CID 1641393.
In theory that will never happen - it's guaranteed that both "reg1" and
"reg2" is non-NULL because we're retrieving them in compile-time from
static arrays. Coverity doesn't know that though.
To make Coverity happier and add a bit more clarity in the code,
g_assert() each token to make it clear that those 2 values aren't
supposed to be NULL ever. Do that in both reg_is_ulong_integer() and
reg_is_u64_fpu().
We're also taking the opportunity to implement suggestions made by Peter
in [1] in both functions:
- use g_strsplit() instead of strtok();
- use g_ascii_strcasecmp() instead of strcasecmp().
[1]
https://lore.kernel.org/qemu-devel/cafeaca_y4bwd9ganbxnpty2mv80vg_jp+a-vkqs5v6f0+bf...@mail.gmail.com/
Coverity: CID 1641393, 1641401
Fixes: e06d209aa6 ("target/riscv: implement MonitorDef HMP API")
Suggested-by: Peter Maydell <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 06e01941ffca3c246a9770f477e43118793fde59
https://github.com/qemu/qemu/commit/06e01941ffca3c246a9770f477e43118793fde59
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: fix riscv_cpu_sirq_pending() mask
We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode
pending interrupts without apparent reason. There's no special treatment
for these ints as far as the spec goes, and this filtering is causing
read_stopi() to miss those VS interrupts [1].
We shouldn't return delegated VS interrupts in S-mode though, so change
the current mask with "~env->hideleg". Note that this is the same
handling we're doing in riscv_cpu_mirq_pending() and env->mideleg.
[1] https://gitlab.com/qemu-project/qemu/-/issues/2820
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: a66d9c37984317cf453a3d1c7341be1d54bb9863
https://github.com/qemu/qemu/commit/a66d9c37984317cf453a3d1c7341be1d54bb9863
Author: Akihiko Odaki <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Fix a uninitialized variable warning
riscv_cpu_validate_v() left its variable, min_vlen, uninitialized if
no vector extension is available, causing a compiler warning.
Re-define riscv_cpu_validate_v() as no-op when no vector extension is
available to prevent the scenario that will read the unintialized
variable by construction. It also simplifies its caller as a bonus.
Signed-off-by: Akihiko Odaki <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 8c9a22b8d626a50985bdd4401013479a71e23f13
https://github.com/qemu/qemu/commit/8c9a22b8d626a50985bdd4401013479a71e23f13
Author: Jay Chang <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg_fields.h.inc
Log Message:
-----------
target/riscv: Make PMP granularity configurable
Previously, the PMP granularity in qemu always used a minimum
granularity of 4 bytes, this patch add pmp-granularity to allow
platforms to configure the value.
A new CPU parameter pmp-granularity has been introduced to the QEMU
command line. For example:
-cpu rv64, g=true, c=true, pmp=true, pmp-granularity=1024
If no specific value is provided, the default value is 4 bytes.
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: eccf20c02a5ad913a910444dc6bbe5de0952d254
https://github.com/qemu/qemu/commit/eccf20c02a5ad913a910444dc6bbe5de0952d254
Author: Jay Chang <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Make PMP CSRs conform to WARL constraints
This patch ensure pmpcfg and pmpaddr comply with WARL constraints.
When the PMP granularity is greater than 4 bytes, NA4 mode is not valid
per the spec and will be silently ignored.
According to the spec, changing pmpcfg.A only affects the "read" value
of pmpaddr. When G > 2 and pmpcfg.A is NAPOT, bits pmpaddr[G-2:0] read
as all ones. When G > 1 and pmpcfg.A is OFF or TOR, bits pmpaddr[G-1:0]
read as all zeros. This allows software to read back the correct
granularity value.
In addition, when updating the PMP address rule in TOR mode,
the start and end addresses of the PMP region should be aligned
to the PMP granularity. (The current SPEC only state in TOR mode
that bits pmpaddr[G-1:0] do not affect the TOR address-matching logic.)
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e8779f3d1509cd07620c6166a9a280376e01ff2f
https://github.com/qemu/qemu/commit/e8779f3d1509cd07620c6166a9a280376e01ff2f
Author: Richard Henderson <[email protected]>
Date: 2025-10-24 (Fri, 24 Oct 2025)
Changed paths:
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/net/cadence_gem.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M include/hw/net/cadence_gem.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/riscv-qmp-cmds.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20251024' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 10.2
* Correct mmu-type property of sifive_u harts in device tree
* Centralize MO_TE uses in a pair of helpers
* Fix Ethernet interface support for microchip-icicle-kit
* Fix mask for smsiaddrcfgh
* Fix env->priv setting in reset_regs_csr()
* Coverity-related fixes
* Fix riscv_cpu_sirq_pending() mask
* Fix a uninitialized variable warning
* Make PMP granularity configurable
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmj6vn4ACgkQr3yVEwxT
# gBORBg/9HMcPIWY4TweyZXcVkcB/4LY3XboBCcumTUO3dEkiVMYc5TDauO++YiyJ
# YPRzFSAgwNxoF2ndtNLSc6OCu6LPRzWpt9a/MavTzfNLOQZ5vUbYCd3g24uR4Plz
# AOt7Jn9l8+95MxGeTq5NfDdOnyC+mF4EiIjhplbZz7UcMpouKRysAibSjuyXlYGD
# DutmQ/bctyDsASNFIl3xwT4po1M4EgMX4nL01ZbfYw2sTjPH2Vj53E0eQ9iZCsP6
# l8L8PEz4Jiad2rapJdm2OS6mirMd3PZbYWqvRga/NQiTs4jGYSxiIhlpqR3Ez2id
# UBGjLKcbsgvyaX1ILq3n6nfftjrXpSEnCMh86/H3xZ8dhA8eBMrGTJvYXAX33ao5
# d3ClcT+E7FTduc+hWl/B/l3eb6fOcEIQ172slBiPEfJJqwJgkXgOfftlxRJQ3iGs
# FbpCL0zEeB1/0SUvgI8Wv5652GiaAljWhhIM7FhWpohc2DxV2iUXuxhhXgHkztwL
# EIddIo9FLQqY7wxlQhvQKRT0hCm/9mtokq6jiQUTuVMn7gf4fWdvDSozRvX1b0DB
# CiJcPnKgM/M4UQHci8rboADWPSJ8oOSdz5dheQfXVNJczFnDqzMMVFbkFicXidJU
# aT+1sPuuSYE6hquR1p4yvxeyyfIQCdffzRBr3WZ2iq7GQ+I4/64=
# =P0/u
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 24 Oct 2025 01:47:10 AM CEST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20251024' of https://github.com/alistair23/qemu: (25
commits)
target/riscv: Make PMP CSRs conform to WARL constraints
target/riscv: Make PMP granularity configurable
target/riscv: Fix a uninitialized variable warning
target/riscv: fix riscv_cpu_sirq_pending() mask
target/riscv/riscv-qmp-cmds.c: coverity-related fixes
target/riscv/kvm: fix env->priv setting in reset_regs_csr()
hw/intc: Allow gaps in hartids for aclint and aplic
aplic: fix mask for smsiaddrcfgh
microchip icicle: Enable PCS on Cadence Ethernet
hw/net/cadence_gem: Add pcs-enabled property
hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO
bus
target/riscv: Introduce mo_endian_env() helper
target/riscv: Introduce mo_endian() helper
target/riscv: Factor MemOp variable out when MO_TE is set
target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc()
target/riscv: Conceal MO_TE within gen_cmpxchg*()
target/riscv: Conceal MO_TE within gen_storepair_tl()
target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx()
target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx()
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/88b1716a4074...e8779f3d1509
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications
