Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 72347b162cb10cc9f6b597f784626b0065d7d5c5
https://github.com/qemu/qemu/commit/72347b162cb10cc9f6b597f784626b0065d7d5c5
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
hw/block/m25p80: Add SFDP table for Winbond W25Q02JVM flash
Add the SFDP data table for Winbond W25Q02JVM flash device. The table
was generated under Linux kernel by dumping the SFDP content using
the following command:
```
hexdump -v -e '8/1 "0x%02x, " "\n"' \
/sys/bus/spi/devices/spi0.0/spi-nor/sfdp
```
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 0d9e8249441cd494fbbece2431a968a1431fd093
https://github.com/qemu/qemu/commit/0d9e8249441cd494fbbece2431a968a1431fd093
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for
AST2600 and AST1030
According to the design of the AST2600, it has a Silicon Revision ID
Register, specifically SCU004 and SCU014, to set the Revision ID for the
AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is
set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was
used for SCU014. The value of "s->silicon_rev" is set by the SoC layer
via the "silicon-rev" property. This patch aligns both SCU004 and SCU014
to use "s->silicon_rev" for consistency and flexibility.
Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed
revision constant ("AST1030_A1_SILICON_REV"). This change updates it to
use the same "s->silicon_rev" property, ensuring that both SoCs follow
a consistent and configurable revision handling mechanism.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: af0a260a04a68ef4de39e052add6e20244795583
https://github.com/qemu/qemu/commit/af0a260a04a68ef4de39e052add6e20244795583
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
hhw/misc/aspeed_scu: Add AST1060 A2 silicon revision definition
Add a new silicon revision constant AST1060_A2_SILICON_REV for the
AST1060 SoC. This allows the SCU model and related SoC layers to
identify and handle AST1060 A2 revision properly in the same way as
other Aspeed SoC families.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8b8cc90cd43fbd72e0979f4edf50680a65ae6955
https://github.com/qemu/qemu/commit/8b8cc90cd43fbd72e0979f4edf50680a65ae6955
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw/arm/aspeed_ast10x0: Add common init function for AST10x0 SoCs
Introduce a new common initialization function
aspeed_soc_ast10x0_init() for AST10x0 series SoCs. This separates the
shared initialization logic from the AST1030-specific part, allowing
reuse by future SoCs such as AST1060.
The AST1060 does not include the LPC and PECI models, so the common
initializer is used for all shared modules, while
aspeed_soc_ast1030_init() adds initialization of LPC and PECI, which
are unique to AST1030.
This refactor improves code reuse and prepares the codebase for
supporting the AST1060 platform.
No functional changes.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 689e04592d51457a2e9da7a2f3d0969a0498f698
https://github.com/qemu/qemu/commit/689e04592d51457a2e9da7a2f3d0969a0498f698
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw/arm/aspeed_ast10x0: Add common realize function for AST10x0 SoCs
Introduce a new common realize function aspeed_soc_ast10x0_realize()
for AST10x0 series SoCs. The shared initialization and realization logic
is now placed in this common function to improve code reuse and reduce
duplication between different SoCs in the same family.
The AST1030 realization function aspeed_soc_ast1030_realize() is
updated to call the new common routine and then perform realization of
its own specific devices such as LPC and PECI, which are not present on
future SoCs like AST1060.
This refactor simplifies maintenance and prepares the framework for
adding AST1060 support.
No functional changes.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 1df0dbdfbbaefd5d27350ef48298d7c12e88b2ed
https://github.com/qemu/qemu/commit/1df0dbdfbbaefd5d27350ef48298d7c12e88b2ed
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw/arm/aspeed_ast10x0: Pass SoC name to common init for AST10x0 family reuse
Refactor the AST10x0 common initialization to accept a socname
parameter.
The AST1030 model can be reused by AST1060 since they share most of the
same controllers. This approach allows AST1060 to leverage the existing
AST1030 initialization flow while keeping separate SoC-specific init
functions for components that differ.
This prepares the framework for AST1060 support, allowing it to reuse
AST1030 device models and initialization flow without code duplication.
No functional changes.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6a8ef87e6b538f6fd6072a731816a144c2413689
https://github.com/qemu/qemu/commit/6a8ef87e6b538f6fd6072a731816a144c2413689
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw/arm/aspeed_ast10x0: Add AST1060 SoC support
Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most
of the AST1030 peripheral device models, as the two SoCs share nearly
the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC,
and SPI.
A new common initialization and realization framework (ast10x0_init
and ast10x0_realize) is leveraged so AST1060 can instantiate the
existing AST1030 models without redefining duplicate device types.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 097957b55594bb9c01a57353092687bc8b0192e0
https://github.com/qemu/qemu/commit/097957b55594bb9c01a57353092687bc8b0192e0
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0_evb.c
Log Message:
-----------
hw/arm/aspeed_ast10x0_evb: Add AST1060 EVB machine support
Add a new machine definition ast1060-evb to support the Aspeed AST1060
evaluation board. The new EVB reuses the same MiniBMC framework used by
AST1030, as both SoCs share the same core peripherals and controller
designs.
The AST1060 EVB machine initializes the ast1060-a2 SoC and sets the
FMC and SPI flash models (w25q80bl and w25q02jvm) for simulation.
This enables QEMU to boot and emulate firmware images for AST1060-based
platforms.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2510e00f2c1eca51856515c9736eb6fc803246a1
https://github.com/qemu/qemu/commit/2510e00f2c1eca51856515c9736eb6fc803246a1
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M tests/functional/arm/meson.build
A tests/functional/arm/test_aspeed_ast1060.py
Log Message:
-----------
tests/functional/arm/test_aspeed_ast1060: Add functional tests for Aspeed
AST1060 SoC
Add functional tests for the Aspeed AST1060 SoC and its evaluation board.
The new test test_aspeed_ast1060.py validates booting the AST1060 EVB
machine using the Zephyr OS and ASPEED PROT application
(ast1060_prot_v03.02.tgz)
and ensures basic console functionality.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ec348addb9a81222d730a808e849089621746bdc
https://github.com/qemu/qemu/commit/ec348addb9a81222d730a808e849089621746bdc
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs/system/arm/aspeed: Update Aspeed and 2700 family boards list
Remove the ast2700-evb entry from the Aspeed family boards list in
the documentation. The AST2700 platform now belongs to the new Aspeed
2700 family group, which has its own dedicated documentation section
and board definitions.
Update the Aspeed 2700 family boards list in the documentation to include
the new ast2700fc board entry.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 641455f526918144c06299dc2ba12255d1360024
https://github.com/qemu/qemu/commit/641455f526918144c06299dc2ba12255d1360024
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs/system/arm/aspeed: Update Aspeed MiniBMC section to include AST1060
processor
Added details describing AST1060 as a Platform Root of Trust processor board
alongside
AST1030 MiniBMC, and extended the list of missing devices to include
SMBus Filter and QSPI Monitor controllers.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3c16b8ea293221eb86db4a7c1ef8bfb8573b0083
https://github.com/qemu/qemu/commit/3c16b8ea293221eb86db4a7c1ef8bfb8573b0083
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add BSM FRU EEPROM
Use ipmitool/frugen tool to generate a BSM image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d684236c6d93163aa93398f4c20a1a4ea05b76b7
https://github.com/qemu/qemu/commit/d684236c6d93163aa93398f4c20a1a4ea05b76b7
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add DC-SCM FRU EEPROM
Use ipmitool/frugen tool to generate a DC-SCM image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 171dc465243a10e7a76821540836f741bb5a12ab
https://github.com/qemu/qemu/commit/171dc465243a10e7a76821540836f741bb5a12ab
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add PDB FRU EEPROM
Use ipmitool/frugen tool to generate a PDB image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b7016ea66f5d846419cdfda9aae6a469749aa1c8
https://github.com/qemu/qemu/commit/b7016ea66f5d846419cdfda9aae6a469749aa1c8
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add OSFP FRU EEPROM
Use ipmitool/frugen tool to generate an OSFP image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: dbf93cb83df018400bcec7a1562fd9c2dbedc826
https://github.com/qemu/qemu/commit/dbf93cb83df018400bcec7a1562fd9c2dbedc826
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add FIO FRU EEPROM
Use ipmitool/frugen tool to generate an FIO image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5a49b57cd51efccfee974c93d450c379c832f8dc
https://github.com/qemu/qemu/commit/5a49b57cd51efccfee974c93d450c379c832f8dc
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add HDD FRU EEPROM
Use ipmitool/frugen tool to generate a HDD image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 121181ca6e73f35670f3b9e29f07922d55ddf9e1
https://github.com/qemu/qemu/commit/121181ca6e73f35670f3b9e29f07922d55ddf9e1
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add GB200 FRU EEPROM
Use ipmitool/frugen tool to generate a GB200 image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3836f5a4db858e0b314cbe58114f3319758448c8
https://github.com/qemu/qemu/commit/3836f5a4db858e0b314cbe58114f3319758448c8
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add GB200-IO FRU EEPROM
Use ipmitool/frugen tool to generate a GB200-IO image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6b160e218a9e6ceca9f56bffd897808e188602d8
https://github.com/qemu/qemu/commit/6b160e218a9e6ceca9f56bffd897808e188602d8
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add HMC FRU EEPROM
Use ipmitool/frugen tool to generate a HMC image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b32fc2f9071b9cb68f6661bee4a1638a05fdd509
https://github.com/qemu/qemu/commit/b32fc2f9071b9cb68f6661bee4a1638a05fdd509
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add NIC FRU EEPROM
Use ipmitool/frugen tool to generate a CX-7 NIC image based on a
sanitized set of data from a real device EEPROM.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d8e135369a363750b4a131ee3e272813f5e9419a
https://github.com/qemu/qemu/commit/d8e135369a363750b4a131ee3e272813f5e9419a
Author: Patrick Williams <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast2600_catalina.c
Log Message:
-----------
hw/arm/aspeed: catalina: add Cable Cartridge FRU EEPROM
Use ipmitool/frugen tool to generate a Cable Cart image based on a
sanitized set of data from a real device EEPROM. The EEPROM
bus/address did not match device tree for one of the EEPROMs so move
it from bus 13 / 55 to bus 12 / 54.
Signed-off-by: Patrick Williams <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5fbe0fc35a3ea39ff089ea6cda86747ebbb68102
https://github.com/qemu/qemu/commit/5fbe0fc35a3ea39ff089ea6cda86747ebbb68102
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
A hw/gpio/aspeed_sgpio.c
M hw/gpio/meson.build
A include/hw/gpio/aspeed_sgpio.h
Log Message:
-----------
hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO
This initial implementation includes the basic device structure,
memory-mapped register definitions, and read/write handlers for the
SGPIO control registers.
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Kane Chen <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8b0265db2751f271ffa3d946e622eb50b2e9b963
https://github.com/qemu/qemu/commit/8b0265db2751f271ffa3d946e622eb50b2e9b963
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/gpio/aspeed_sgpio.c
Log Message:
-----------
hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins
The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
implemented to get and set the level of individual SGPIO pins. These
are then exposed as boolean properties on the SGPIO device object.
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Kane Chen <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 362d551dee7e50f7d8046c44496010d3e1297a48
https://github.com/qemu/qemu/commit/362d551dee7e50f7d8046c44496010d3e1297a48
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/gpio/aspeed_sgpio.c
M include/hw/gpio/aspeed_sgpio.h
Log Message:
-----------
hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling
The SGPIO controller can generate interrupts based on various pin state
changes, such as rising/falling edges or high/low levels. This change
adds the necessary logic to detect these events, update the interrupt
status registers, and signal the interrupt to the SoC.
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Kane Chen <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 46ad43a03191959409312b3a6ff522785894c712
https://github.com/qemu/qemu/commit/46ad43a03191959409312b3a6ff522785894c712
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers
This commit updates the Aspeed SoC model to support two SGPIO
controllers, reflecting the hardware capabilities of the AST2700
The memory map and interrupt map are updated to include entries for
two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a
prerequisite for the full implementation of the SGPIO device model.
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 508e8630de390bd9183b1bcc3bb9747188245a32
https://github.com/qemu/qemu/commit/508e8630de390bd9183b1bcc3bb9747188245a32
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC
This commit integrates the Aspeed SGPIO controller into the AST2700
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: eb5f781adde3a1ef1e6241d8c19949afce110a64
https://github.com/qemu/qemu/commit/eb5f781adde3a1ef1e6241d8c19949afce110a64
Author: Yubin Zou <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
A tests/qtest/ast2700-sgpio-test.c
M tests/qtest/meson.build
Log Message:
-----------
test/qtest: Add Unit test for Aspeed SGPIO
This commit introduces a new qtest for the Aspeed SGPIO controller
The test covers the following:
- Setting and clearing SGPIO output pins and verifying the pin state.
- Setting and clearing SGPIO input pins and verifying the pin state.
- Verifying that level-high interrupts are correctly triggered and cleared.
Signed-off-by: Yubin Zou <[email protected]>
Reviewed-by: Kane Chen <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 75bcfb98a13d14beb2ea95fb3c51da01c7102325
https://github.com/qemu/qemu/commit/75bcfb98a13d14beb2ea95fb3c51da01c7102325
Author: Cédric Le Goater <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M tests/functional/arm/test_aspeed_gb200nvl_bmc.py
Log Message:
-----------
tests/functional: Fix URL of gb200nvl-bmc image
Commit [1] moved the FW image of the gb200nvl-bmc machine and broke
the associated functional test. Fix that.
[1]
https://github.com/legoater/qemu-aspeed-boot/commit/52451b2472eeb40aa97e131aeea327e9d4a8a78a
Cc: Ed Tanous <[email protected]>
Cc: Patrick Williams <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: e50a021a451a33da0474a57b5435d4cf6e7d8c1c
https://github.com/qemu/qemu/commit/e50a021a451a33da0474a57b5435d4cf6e7d8c1c
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/arm/aspeed_ast27x0_evb.c
Log Message:
-----------
hw/arm: Remove ast2700a0-evb machine
The ast2700a0-evb machine represents the first revision of the AST2700 and
serves as the initial engineering sample rather than a production version.
A newer revision, A1, is now supported, and the ast2700a1-evb should replace
the older A0 version.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
[ clg: Updated docs/about/removed-features.rst ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 4f53de2f103d6dfb5ad0498995d91a9694f40dd2
https://github.com/qemu/qemu/commit/4f53de2f103d6dfb5ad0498995d91a9694f40dd2
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC
The ast2700-a1 SOC represented the first revision of the AST2700 and
was intended as an early engineering sample rather than a production
platform. A newer revision, A1, is now supported, and the ast2700-a1
SOC should replace the older A0 version.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 14ecbe9fb27f9f954f6c937a6e98c3eb39433c75
https://github.com/qemu/qemu/commit/14ecbe9fb27f9f954f6c937a6e98c3eb39433c75
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Remove GIC 128 - 136
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 798c442df75617071e66e32923988f6a87728aa8
https://github.com/qemu/qemu/commit/798c442df75617071e66e32923988f6a87728aa8
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M docs/specs/aspeed-intc.rst
Log Message:
-----------
docs/specs/aspeed-intc: Remove GIC 128 - 136
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 61fa20dc50feab20cb72441cdbcf62e63b27a53b
https://github.com/qemu/qemu/commit/61fa20dc50feab20cb72441cdbcf62e63b27a53b
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast27x0-ssp.c
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Remove SSP 128 - 138
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d1736a2ae2999436b07ccdbef20719774c936189
https://github.com/qemu/qemu/commit/d1736a2ae2999436b07ccdbef20719774c936189
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/arm/aspeed_ast27x0-tsp.c
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Remove TSP 128 - 138
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9cbd8ee7f67fceee51d3c993a282e5adc397b6b9
https://github.com/qemu/qemu/commit/9cbd8ee7f67fceee51d3c993a282e5adc397b6b9
Author: Jamin Lin <[email protected]>
Date: 2026-01-05 (Mon, 05 Jan 2026)
Changed paths:
M hw/i2c/aspeed_i2c.c
Log Message:
-----------
hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first
In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) based on
the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_ADDR
(0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if the
firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR.
If the firmware instead set I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR before setting
I2CM_DMA_LEN, the value written to I2CC_DMA_LEN would be incorrect.
To fix this issue, the model should be updated to set I2CC_DMA_LEN when the
firmware writes to the I2CM_DMA_LEN register, rather than when it writes to the
I2CM_DMA_RX_ADDR and I2CM_DMA_TX_ADDR registers.
Signed-off-by: Jamin Lin <[email protected]>
Fixes: ba2cccd64e90 ("aspeed: i2c: Add new mode support")
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 0fc482b73d8e085d1375b4e17b0647fd2e6fe8f0
https://github.com/qemu/qemu/commit/0fc482b73d8e085d1375b4e17b0647fd2e6fe8f0
Author: Richard Henderson <[email protected]>
Date: 2026-01-06 (Tue, 06 Jan 2026)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M docs/specs/aspeed-intc.rst
M docs/system/arm/aspeed.rst
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast10x0_evb.c
M hw/arm/aspeed_ast2600_catalina.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_ast27x0_evb.c
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
A hw/gpio/aspeed_sgpio.c
M hw/gpio/meson.build
M hw/i2c/aspeed_i2c.c
M hw/intc/aspeed_intc.c
M hw/misc/aspeed_scu.c
M include/hw/arm/aspeed_soc.h
A include/hw/gpio/aspeed_sgpio.h
M include/hw/misc/aspeed_scu.h
M tests/functional/arm/meson.build
A tests/functional/arm/test_aspeed_ast1060.py
M tests/functional/arm/test_aspeed_gb200nvl_bmc.py
A tests/qtest/ast2700-sgpio-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Removed the ast2700-a0 SoC and ast2700a0-evb machine.
* Added SGPIO support to the ast2700 SoC, including unit tests.
* Added several FRU EEPROMs to the Catalina board.
* Added support for the new AST1060 SoC and ast1060-evb machine,
including functional tests.
* Fixed the silicon revision ID register for AST2600 and AST1030 SoCs.
* Added an SFDP table for a Winbond flash chip.
* Updated documentation for Aspeed boards.
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# gpg: aka "Cédric Le Goater <[email protected]>" [full]
* tag 'pull-aspeed-20260105' of https://github.com/legoater/qemu: (36 commits)
hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first
hw/intc/aspeed: Remove TSP 128 - 138
hw/intc/aspeed: Remove SSP 128 - 138
docs/specs/aspeed-intc: Remove GIC 128 - 136
hw/intc/aspeed: Remove GIC 128 - 136
hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC
hw/arm: Remove ast2700a0-evb machine
tests/functional: Fix URL of gb200nvl-bmc image
test/qtest: Add Unit test for Aspeed SGPIO
hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC
hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers
hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling
hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins
hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO
hw/arm/aspeed: catalina: add Cable Cartridge FRU EEPROM
hw/arm/aspeed: catalina: add NIC FRU EEPROM
hw/arm/aspeed: catalina: add HMC FRU EEPROM
hw/arm/aspeed: catalina: add GB200-IO FRU EEPROM
hw/arm/aspeed: catalina: add GB200 FRU EEPROM
hw/arm/aspeed: catalina: add HDD FRU EEPROM
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/159107e39060...0fc482b73d8e
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