On Saturday 14 May 2005 10:37, Blue Swirl wrote: > Hi, > > The architecture used in sparc target (sun4m) supports SMP up to a maximum > of 16 CPUs. At hardware emulation level (hw/*, target-sparc/*), it would be > easy to add the missing interprocessor interrupts, per-CPU counters and > atomic instructions. It would also be simple to add the prom functions for > starting/stopping CPUs to Proll. Maybe some days' work in total. > > Higher level (vl.c, cpu-exec.c) could need more work. Maybe Fabrice can > enlighten us?
I guess you'd really want to simulate multiple CPUs with multiple host threads. One of the additional problems could then be memory/cache coherency. I'm not sure how much of a problem this would be in practice. If both host and guest require the same (or no) explicit SMP memory barriert it's not a problem. It the guest has stronger coherency requirements than the host we have a problem. > For some reason, Sparc performance is low (1/10 of native x86 nbench) > compared to x86 (2/3). Simulating SMP on a uniprocessor would only decrease > performance. It think x86-on-x86 user-mode uses code-copying by default. ie. it runs a lot of the the code unmodified. In my experience i386-softmmu is generally 10-15x slower than native, and arm-user is 5-10x slower. Paul _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
