This patch was created by Juergen Kiel, so to be clear I did not make this
patch.
I did however, test it, with the current CVS code, and this patch to the ACPI
tables does allow a floppy drive to be seen by a Solaris 10/X86 guest.
Prior to this time, changes in Solaris 10 do not correctly enumerate the ISA
bus for the floppy, and therefore you could never add an Install Time Update
(ITU), such as the DiskUpdate on tools.de/solaris/itu/DU.zip which has a
modifed RTL8029 driver that works with Qemu on SolarisX86. Obviosly, if
you boot a Solaris 10/x86 install with -B acpi-user-options=0x0, you will not
see the floppy. (I see that a patch is in the works for OpenSolaris, so
eventually
this will be fixed for good on Solaris).
Juergen comments:
I've experimented with the attached patch to add the PS/2 floppy controller,
serial and parallel ports to qemu-cvs's acpi tables, so that a Solaris x86
guest OS will see the /dev/diskette device.
Note: the file hw/acpi-dsdt.hex must be rebuilt using Intel's "iasl"
ACPI compiler. In the hw directory, run "iasl -tc acpi-dsdt.dsl". That
should build the acpi-dsdt.hex file from acpi-dsdt.dsl.
Ben
diff -ru /tmp/qemu-cvs/hw/acpi-dsdt.dsl ./hw/acpi-dsdt.dsl
--- /tmp/qemu-cvs/hw/acpi-dsdt.dsl 2006-05-04 01:13:13.000000000 +0200
+++ ./hw/acpi-dsdt.dsl 2006-05-14 20:21:02.046226910 +0200
@@ -161,8 +161,9 @@
}
}
- /* PIIX3 ISA bridge */
Scope(\_SB.PCI0) {
+
+ /* PIIX3 ISA bridge */
Device (ISA) {
Name (_ADR, 0x00010000)
@@ -202,6 +203,7 @@
}
}
+ /* PS/2 mouse */
Device (MOU)
{
Name (_HID, EisaId ("PNP0F13"))
@@ -219,7 +221,132 @@
Return (TMP)
}
}
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+
+ /* Parallel port */
+ Device (LPT)
+ {
+ Name (_HID, EisaId ("PNP0400"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Store (\_SB.PCI0.PX13.DRSA, Local0)
+ And (Local0, 0x80000000, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
+ IRQNoFlags () {7}
+ })
+ Return (BUF0)
+ }
+ }
+
+ /* Serial Ports */
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ Store (\_SB.PCI0.PX13.DRSC, Local0)
+ And (Local0, 0x08000000, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+ IRQNoFlags () {4}
+ })
+ Return (BUF0)
+ }
+ }
+
+ Device (COM2)
+ {
+ Name (_HID, EisaId ("PNP0501"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Store (\_SB.PCI0.PX13.DRSC, Local0)
+ And (Local0, 0x80000000, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+ IRQNoFlags () {3}
+ })
+ Return (BUF0)
+ }
+ }
}
+
+ /* PIIX4 PM */
+ Device (PX13) {
+ Name (_ADR, 0x00010003)
+
+ OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
+ Field (P13C, DWordAcc, NoLock, Preserve)
+ {
+ DRSA, 32,
+ DRSB, 32,
+ DRSC, 32,
+ DRSE, 32,
+ DRSF, 32,
+ DRSG, 32,
+ DRSH, 32,
+ DRSI, 32,
+ DRSJ, 32
+ }
+ }
}
/* PCI IRQs */
diff -ru /tmp/qemu-cvs/hw/acpi.c ./hw/acpi.c
--- /tmp/qemu-cvs/hw/acpi.c 2006-05-08 15:38:46.000000000 +0200
+++ ./hw/acpi.c 2006-05-14 18:53:08.528614455 +0200
@@ -241,7 +241,6 @@
pci_conf[0x0b] = 0x06; // bridge device
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x01; // interrupt pin 1
- pci_conf[0x60] = 0x10; // release number
pm_io_base = PM_IO_BASE;
pci_conf[0x40] = pm_io_base | 1;
@@ -254,6 +253,11 @@
register_ioport_write(SMI_CMD_IO_ADDR, 1, 1, smi_cmd_writeb, s);
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
+ pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
+ pci_conf[0x63] = 0x60;
+ pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
+ (serial_hds[1] != NULL ? 0x90 : 0);
+
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
piix4_pm_state = s;
}
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