On Tuesday 12 September 2006 14:19, Markus Schiltknecht wrote:
> Paul Brook wrote:
> > Modern CPUs are complicated, with many factors effecting execution speed
> > (pipeline interlocks, multiple levels of cache). A cycle accurate
> > simulator will generally be orders of magnitude slower than qemu.
>
> Would it be feasible to just limit the number of instructions qemu
> simulates? Of course that's not very precise and most probably far from
> cycle accurate. But it would allow to easily scale down a virtual
> machine. Which then would allow comparable benchmarks or such.
>
> One step, somewhat more accurate would be to weight all the different
> assembler commands with known (measured) average execution times. Taking
> into account 40% cache misses, for example. (Hm.. but since cache misses
> are very expensive, that might not lead to a much better approximation,
> I guess)

I'd be surprised if you managed to get any sort of reliable results.
Most of what you described can be achieved with profiling and static analysis.

You could maybe get order-of-magnitude estimates (ie. do you need a 20MHz cpu 
or a 2GHz cpu), but I certainly wouldn't trust the results for deciding 
between eg. 500MHz and 200MHz cores.

IMHO a benchmarking setup that doesn't reliably correspond to real system 
performance is worse than useless.

Paul


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