Latest revision of LoongArch ISA is out at https://www.loongson.cn/uploads/images/2023102309132647981.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%84%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C%E5%8D%B7%E4%B8%80_r1p10.pdf (Chinese only). The revision includes the following updates:
- estimated fp reciporcal instructions: frecip -> frecipe, frsqrt -> frsqrte - 128-bit width store-conditional instruction: sc.q - ll.w/d with acquire semantic: llacq.w/d, sc.w/d with release semantic: screl.w/d - compare and swap instructions: amcas[_db].b/w/h/d - byte and word-wide amswap/add instructions: am{swap/add}[_db].{b/h} - new definition for dbar hints - clarify 32-bit division instruction hebavior - clarify load ordering when accessing the same address - introduce message signaled interrupt - introduce hardware page table walker The new revision is implemented in the to be released Loongson 3A6000 processor. This patch series implements the new instructions except sc.q, because I do not know how to match a pair of ll.d to sc.q. Jiajie Chen (5): include/exec/memop.h: Add MO_TESB target/loongarch: Add am{swap/add}[_db].{b/h} target/loongarch: Add amcas[_db].{b/h/w/d} target/loongarch: Add estimated reciprocal instructions target/loongarch: Add llacq/screl instructions include/exec/memop.h | 1 + target/loongarch/cpu.h | 4 ++ target/loongarch/disas.c | 32 ++++++++++++ .../loongarch/insn_trans/trans_atomic.c.inc | 52 +++++++++++++++++++ .../loongarch/insn_trans/trans_farith.c.inc | 4 ++ target/loongarch/insn_trans/trans_vec.c.inc | 8 +++ target/loongarch/insns.decode | 32 ++++++++++++ target/loongarch/translate.h | 27 +++++++--- 8 files changed, 152 insertions(+), 8 deletions(-) -- 2.42.0