On 10/23/23 08:29, Jiajie Chen wrote:
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
@@ -17,6 +17,14 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
return true;
}
+static bool gen_llacq(DisasContext *ctx, arg_rr *a, MemOp mop)
+{
+ arg_rr_i tmp_a = {
+ .rd = a->rd, .rj = a->rj, .imm = 0
+ };
+ return gen_ll(ctx, &tmp_a, mop);
+}
+
static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
@@ -45,6 +53,14 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
return true;
}
+static bool gen_screl(DisasContext *ctx, arg_rr *a, MemOp mop)
+{
+ arg_rr_i tmp_a = {
+ .rd = a->rd, .rj = a->rj, .imm = 0
+ };
+ return gen_sc(ctx, &tmp_a, mop);
+}
This is incorrect. You need to add the required memory barriers.
Should be like
- static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool acq)
{
...
+ if (acq) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
return true;
}
- static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel)
{
...
+ if (rel) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
...
}
TRANS(ll_w, ALL, gen_ll, MO_TESL, false)
TRANS(sc_w, ALL, gen_sc, MO_TESL, false)
TRANS(ll_d, 64, gen_ll, MO_TEUQ, false)
TRANS(sc_d, 64, gen_sc, MO_TEUQ, false)
TRANS(llacq_w, LLACQ_SCREL, gen_ll, MO_TESL, true)
TRANS(screl_w, LLACQ_SCREL, gen_sc, MO_TESL, true)
TRANS(llacq_d, LLACQ_SCREL_64, gen_ll, MO_TEUQ, true)
TRANS(screl_d, LLACQ_SCREL_64, gen_sc, MO_TEUQ, true)
You should decode into a common argument format, rather than doing it by hand.
@rr_i0 .... ........ ..... ..... rj:5 rd:5 &rr_i imm=0
llacq_w 0011 10000101 01111 00000 ..... ..... @rr_i0
screl_w 0011 10000101 01111 00001 ..... ..... @rr_i0
llacq_d 0011 10000101 01111 00010 ..... ..... @rr_i0
screl_d 0011 10000101 01111 00011 ..... ..... @rr_i0
r~
