This patchset updates the RISC-V vector cryptography support to the ratified version v1.0.0 (commit 1769c26, released on 2023/10).
v2: - Fixed the instruction order at disassembler part. - Fixed the vror.vi disassembler format. - Verified by code examples provided by vector crypto spec repository (riscv-crypto). - Rebased to riscv-to-apply.next branch (1f910f3) v1: - Support Zvkb, Zvkt, and other shorthand extensions(Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg). - Support the disassembler for vector crypto extensions. - Moved vector crypto extensions from experimental extensions to ratified extensions. - Replaced TAB indentations with spaces in disas/riscv.c. Max Chou (14): target/riscv: Add cfg property for Zvkt extension target/riscv: Expose Zvkt extension property target/riscv: Add cfg property for Zvkb extension target/riscv: Replace Zvbb checking by Zvkb target/riscv: Expose Zvkb extension property target/riscv: Add cfg properties for Zvkn[c|g] extensions target/riscv: Expose Zvkn[c|g] extnesion properties target/riscv: Add cfg properties for Zvks[c|g] extensions target/riscv: Expose Zvks[c|g] extnesion properties target/riscv: Move vector crypto extensions to riscv_cpu_extensions disas/riscv: Add rv_fmt_vd_vs2_uimm format disas/riscv: Add rv_codec_vror_vi for vror.vi disas/riscv: Add support for vector crypto extensions disas/riscv: Replace TABs with space disas/riscv.c | 157 ++++++++++++++++++++++- disas/riscv.h | 2 + target/riscv/cpu.c | 36 ++++-- target/riscv/cpu_cfg.h | 8 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 37 ++++-- target/riscv/tcg/tcg-cpu.c | 48 ++++++- 6 files changed, 258 insertions(+), 30 deletions(-) -- 2.34.1
