Currently the available PMU counters start at HPM3 and run through to the number specified by the "pmu-num" property. There is no requirement in the specification that the available counters be continously numbered. This series add suppport for specifying a discountinuous range of counters though a "pmu-mask" property.
v5: * Added more R-B tags * Make "pmu-num" property directly update "pmu-mask" removing the need to store that value. v4: * Added more R-B tags (just missing from 4 & 5) * Added details on how to calculate mask * Use custom property for "pmu-num" in order to give deprecation warning * Special case a zero value for "pmu-num" v3: * Use env_archcpu() in csr.c * Re-added check to enforce deprectated "pmu-num" below limit * Check that standard counters are not included in mask * Remove use of MAKE_32BIT_MASK() v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (5): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Use existing PMU counter mask in FDT generation target/riscv: Add "pmu-mask" property to replace "pmu-num" docs/about/deprecated: Document RISC-V "pmu-num" deprecation docs/about/deprecated.rst | 12 ++++++++++++ hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++++- target/riscv/cpu_cfg.h | 2 +- target/riscv/csr.c | 5 +++-- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 34 ++++++++++++++------------------ target/riscv/pmu.h | 5 +++-- target/riscv/tcg/tcg-cpu.c | 10 ++++++++-- 9 files changed, 83 insertions(+), 29 deletions(-) -- 2.41.0
