On Mon, Dec 18, 2023 at 10:56 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, > comes with a lot of defaults. This is fine for most regular uses but > it's not suitable when more control of what is actually loaded in the > CPU is required. > > A bare-bones CPU would be annoying to deal with if not by profile > support, a way to load a multitude of extensions with a single flag. > Profile support is going to be implemented shortly, so let's add a CPU > for it. > > The new 'rv64i' CPU will have only RVI loaded. It is inspired in the > profile specification that dictates, for RVA22U64 [1]: > > "RVA22U64 Mandatory Base > RV64I is the mandatory base ISA for RVA22U64" > > And so it seems that RV64I is the mandatory base ISA for all profiles > listed in [1], making it an ideal CPU to use with profile support. > > rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features > from pre-existent CPUs: > > - it allows extensions to be enabled, like generic CPUs; > - it will not inherit extension defaults, like vendor CPUs. > > This is the minimum extension set to boot OpenSBI and buildroot using > rv64i: > > ./build/qemu-system-riscv64 -nographic -M virt \ > -cpu rv64i,sv39=true,g=true,c=true,s=true,u=true > > Our minimal riscv,isa in this case will be: > > # cat /proc/device-tree/cpus/cpu@0/riscv,isa > rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd# > > [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu-qom.h | 2 ++ > target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 48 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index ca7dd509e3..4d1aa54311 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -24,6 +24,7 @@ > #define TYPE_RISCV_CPU "riscv-cpu" > #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" > #define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" > +#define TYPE_RISCV_BARE_CPU "riscv-bare-cpu" > > #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU > #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) > @@ -33,6 +34,7 @@ > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") > +#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index bb91bcacee..34102f6869 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -370,6 +370,17 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, > /* Set the satp mode to the max supported */ > static void set_satp_mode_default_map(RISCVCPU *cpu) > { > + /* > + * Bare CPUs do not default to the max available. > + * Users must set a valid satp_mode in the command > + * line. > + */ > + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) != NULL) { > + warn_report("No satp mode set. Defaulting to 'bare'"); > + cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE); > + return; > + } > + > cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; > } > #endif > @@ -552,6 +563,28 @@ static void rv128_base_cpu_init(Object *obj) > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); > #endif > } > + > +static void rv64i_bare_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + riscv_cpu_set_misa(env, MXL_RV64, RVI); > + > + /* Remove the defaults from the parent class */ > + RISCV_CPU(obj)->cfg.ext_zicntr = false; > + RISCV_CPU(obj)->cfg.ext_zihpm = false; > + > + /* Set to QEMU's first supported priv version */ > + env->priv_ver = PRIV_VERSION_1_10_0; > + > + /* > + * Support all available satp_mode settings. The default > + * value will be set to MBARE if the user doesn't set > + * satp_mode manually (see set_satp_mode_default()). > + */ > +#ifndef CONFIG_USER_ONLY > + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); > +#endif > +} > #else > static void rv32_base_cpu_init(Object *obj) > { > @@ -1785,6 +1818,13 @@ void riscv_cpu_list(void) > .instance_init = initfn \ > } > > +#define DEFINE_BARE_CPU(type_name, initfn) \ > + { \ > + .name = type_name, \ > + .parent = TYPE_RISCV_BARE_CPU, \ > + .instance_init = initfn \ > + } > + > static const TypeInfo riscv_cpu_type_infos[] = { > { > .name = TYPE_RISCV_CPU, > @@ -1807,6 +1847,11 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .parent = TYPE_RISCV_CPU, > .abstract = true, > }, > + { > + .name = TYPE_RISCV_BARE_CPU, > + .parent = TYPE_RISCV_CPU, > + .abstract = true, > + }, > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), > #if defined(TARGET_RISCV32) > @@ -1823,6 +1868,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), > #endif > }; > > -- > 2.43.0 > >