On Wed, 10 Jan 2024 at 23:42, Nabih Estefan <nabiheste...@google.com> wrote: > > From: Hao Wu <wuhao...@google.com> > > The PCI Mailbox Module is a high-bandwidth communcation module > between a Nuvoton BMC and CPU. It features 16KB RAM that are both > accessible by the BMC and core CPU. and supports interrupt for > both sides. > > This patch implements the BMC side of the PCI mailbox module. > Communication with the core CPU is emulated via a chardev and > will be in a follow-up patch. > > Change-Id: Iaca22f81c4526927d437aa367079ed038faf43f2 > Signed-off-by: Hao Wu <wuhao...@google.com> > Signed-off-by: Nabih Estefan <nabiheste...@google.com> > Reviewed-by: Tyrone Ting <kft...@nuvoton.com> > --- > hw/arm/npcm7xx.c | 15 +-
This patch shouldn't be changing this file: all the code that adds the device to the SoC should be in one patch (patch 2). > hw/misc/meson.build | 1 + > hw/misc/npcm7xx_pci_mbox.c | 324 +++++++++++++++++++++++++++++ > hw/misc/trace-events | 5 + > include/hw/arm/npcm7xx.h | 1 + Similarly the line adding the include to the SoC's header is part of patch 2. > include/hw/misc/npcm7xx_pci_mbox.h | 81 ++++++++ > 6 files changed, 426 insertions(+), 1 deletion(-) > create mode 100644 hw/misc/npcm7xx_pci_mbox.c > create mode 100644 include/hw/misc/npcm7xx_pci_mbox.h thanks -- PMM
