Introduced a 3-layer cache for the ARM virtual machine. Signed-off-by: Sia Jee Heng <jeeheng....@starfivetech.com> --- hw/arm/virt-acpi-build.c | 44 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 17aeec7a6f..c57067cd63 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -426,6 +426,48 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) g_array_free(its_idmaps, true); } +static void pptt_setup(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id) +{ + CPUCaches default_cache_info = { + .l1d_cache = &(CPUCacheInfo) { + .type = DATA_CACHE, + .size = 64 * KiB, + .line_size = 64, + .associativity = 4, + .sets = 256, + .attributes = 0x02, + }, + .l1i_cache = &(CPUCacheInfo) { + .type = INSTRUCTION_CACHE, + .size = 64 * KiB, + .line_size = 64, + .associativity = 4, + .sets = 256, + .attributes = 0x04, + }, + .l2_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .size = 2048 * KiB, + .line_size = 64, + .associativity = 8, + .sets = 4096, + .attributes = 0x0a, + }, + .l3_cache = &(CPUCacheInfo) { + .type = UNIFIED_CACHE, + .size = 4096 * KiB, + .line_size = 64, + .associativity = 8, + .sets = 8192, + .attributes = 0x0a, + }, + }; + + build_pptt(table_data, linker, ms, oem_id, oem_table_id, + &default_cache_info); +} + /* * Serial Port Console Redirection Table (SPCR) * Rev: 1.07 @@ -912,7 +954,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (!vmc->no_cpu_topology) { acpi_add_table(table_offsets, tables_blob); - build_pptt(tables_blob, tables->linker, ms, + pptt_setup(tables_blob, tables->linker, ms, vms->oem_id, vms->oem_table_id); } -- 2.34.1