On Mon, 29 Jan 2024 at 11:08, Jonathan Cameron <jonathan.came...@huawei.com> wrote: > > On Mon, 29 Jan 2024 00:14:23 -0800 > Sia Jee Heng <jeeheng....@starfivetech.com> wrote: > > > Introduced a 3-layer cache for the ARM virtual machine. > > > > Signed-off-by: Sia Jee Heng <jeeheng....@starfivetech.com> > > There are a bunch of CPU registers that also need updating to reflect the > described cache. > https://lore.kernel.org/qemu-devel/20230808115713.2613-3-jonathan.came...@huawei.com/ > It's called HACK for a reason ;) > But there is some discussion about this issue in the thread. > > The l1 etc also needs to reflect the CPU model. This stuff needs to match. > Wrong information being passed to a VM is probably worse than no information.
Yes. The ACPI table information, if we provide it, should be being generated from the CPU cache ID registers. But I'm a bit confused about why the ACPI table has the cache topology in it -- can't the guest read the cache ID registers and figure it out for itself? thanks -- PMM
