Instantiate TYPE_ICH9_LPC_DEVICE in TYPE_ICH9_SOUTHBRIDGE.
Expose the SMM property so the Q35 machine can disable it
(depending on the accelerator used).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
include/hw/southbridge/ich9.h | 4 ----
hw/i386/pc_q35.c | 12 +++---------
hw/isa/lpc_ich9.c | 3 +++
hw/southbridge/ich9.c | 14 ++++++++++++++
hw/i386/Kconfig | 1 -
hw/southbridge/Kconfig | 1 +
6 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h
index d6c3b5ece3..a8da4a8665 100644
--- a/include/hw/southbridge/ich9.h
+++ b/include/hw/southbridge/ich9.h
@@ -16,10 +16,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE)
#define ICH9_PCIE_DEV 28
#define ICH9_PCIE_FUNC_MAX 6
-/* D31:F1 LPC controller */
-#define ICH9_LPC_DEV 31
-#define ICH9_LPC_FUNC 0
-
#define ICH9_GPIO_GSI "gsi"
#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 573a5a0bc0..0fe43e8e2d 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -50,7 +50,6 @@
#include "hw/ide/ahci-pci.h"
#include "hw/intc/ioapic.h"
#include "hw/southbridge/ich9.h"
-#include "hw/isa/ich9_lpc.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/numa.h"
@@ -69,7 +68,6 @@ static void pc_q35_init(MachineState *machine)
Object *phb;
PCIBus *host_bus;
DeviceState *ich9;
- PCIDevice *lpc;
Object *lpc_obj;
DeviceState *lpc_dev;
BusState *idebus[2] = { };
@@ -181,6 +179,7 @@ static void pc_q35_init(MachineState *machine)
object_property_set_link(OBJECT(ich9), "mch-pcie-bus",
OBJECT(host_bus), &error_abort);
qdev_prop_set_bit(ich9, "d2p-enabled", false);
+ qdev_prop_set_bit(ich9, "smm-enabled", x86_machine_is_smm_enabled(x86ms));
qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled);
qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled);
/* Should we create 6 UHCI according to ich9 spec? */
@@ -191,13 +190,8 @@ static void pc_q35_init(MachineState *machine)
gsi_state = pc_gsi_create(&x86ms->gsi, true);
/* create ISA bus */
- lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
- TYPE_ICH9_LPC_DEVICE);
- lpc_obj = OBJECT(lpc);
- lpc_dev = DEVICE(lpc);
- qdev_prop_set_bit(lpc_dev, "smm-enabled",
- x86_machine_is_smm_enabled(x86ms));
- pci_realize_and_unref(lpc, host_bus, &error_fatal);
+ lpc_obj = object_resolve_path_component(OBJECT(ich9), "lpc");
+ lpc_dev = DEVICE(lpc_obj);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 685ac38c72..4d7b5c0c64 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -55,6 +55,9 @@
#include "hw/acpi/acpi_aml_interface.h"
#include "trace.h"
+#define ICH9_LPC_DEV 31
+#define ICH9_LPC_FUNC 0
+
#define ICH9_A2_LPC_REVISION 0x2
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c
index 085d75e569..57a05b35e1 100644
--- a/hw/southbridge/ich9.c
+++ b/hw/southbridge/ich9.c
@@ -13,6 +13,7 @@
#include "hw/southbridge/ich9.h"
#include "hw/pci/pci.h"
#include "hw/pci-bridge/ich_dmi_pci.h"
+#include "hw/isa/ich9_lpc.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide.h"
#include "hw/i2c/smbus_ich9.h"
@@ -21,6 +22,7 @@
#include "hw/usb/hcd-uhci.h"
#define ICH9_D2P_DEVFN PCI_DEVFN(30, 0)
+#define ICH9_LPC_DEVFN PCI_DEVFN(31, 0)
#define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2)
#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3)
#define ICH9_EHCI_FUNC 7
@@ -34,6 +36,7 @@ struct ICH9State {
I82801b11Bridge d2p;
AHCIPCIState sata0;
+ ICH9LPCState lpc;
ICH9SMBState smb;
EHCIPCIState ehci[EHCI_PER_FN];
UHCIState uhci[EHCI_PER_FN * UHCI_PER_FN];
@@ -148,6 +151,13 @@ static bool ich9_realize_usb(ICH9State *s, Error **errp)
static void ich9_init(Object *obj)
{
+ ICH9State *s = ICH9_SOUTHBRIDGE(obj);
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ICH9_LPC_DEVICE);
+ qdev_prop_set_int32(DEVICE(&s->lpc), "addr", ICH9_LPC_DEVFN);
+ qdev_prop_set_bit(DEVICE(&s->lpc), "multifunction", true);
+ object_property_add_alias(obj, "smm-enabled",
+ OBJECT(&s->lpc), "smm-enabled");
}
static void ich9_realize(DeviceState *dev, Error **errp)
@@ -163,6 +173,10 @@ static void ich9_realize(DeviceState *dev, Error **errp)
return;
}
+ if (!qdev_realize(DEVICE(&s->lpc), BUS(s->pci_bus), errp)) {
+ return;
+ }
+
if (s->sata_enabled && !ich9_realize_sata(s, errp)) {
return;
}
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 226d7f6916..eccc834e49 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -100,7 +100,6 @@ config Q35
select PC_ACPI
select PCI_EXPRESS_Q35
select ICH9
- select LPC_ICH9
select DIMM
select SMBIOS
select FW_CFG_DMA
diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig
index 31eb125bf7..8ce62b703c 100644
--- a/hw/southbridge/Kconfig
+++ b/hw/southbridge/Kconfig
@@ -8,3 +8,4 @@ config ICH9
select ACPI_ICH9
imply USB_EHCI_PCI
imply USB_UHCI
+ select LPC_ICH9
--
2.41.0
