Start the TYPE_ICH9_SOUTHBRIDGE stub, a kind of QOM
container which will contain all the ICH9 parts.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
MAINTAINERS | 1 +
include/hw/southbridge/ich9.h | 3 ++
hw/i386/pc_q35.c | 7 ++++
hw/southbridge/ich9.c | 61 +++++++++++++++++++++++++++++++++++
hw/Kconfig | 1 +
hw/i386/Kconfig | 1 +
hw/meson.build | 1 +
hw/southbridge/Kconfig | 5 +++
hw/southbridge/meson.build | 3 ++
9 files changed, 83 insertions(+)
create mode 100644 hw/southbridge/ich9.c
create mode 100644 hw/southbridge/Kconfig
create mode 100644 hw/southbridge/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index 50507c3dd6..d1a2eddd4c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2608,6 +2608,7 @@ S: Supported
F: hw/acpi/ich9*.c
F: hw/i2c/smbus_ich9.c
F: hw/isa/lpc_ich9.c
+F: hw/southbridge/ich9.c
F: include/hw/acpi/ich9*.h
F: include/hw/pci-bridge/ich_dmi_pci.h
F: include/hw/southbridge/ich9.h
diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h
index b2abf483e0..162ae3baa1 100644
--- a/include/hw/southbridge/ich9.h
+++ b/include/hw/southbridge/ich9.h
@@ -11,6 +11,9 @@
#include "qemu/notify.h"
#include "qom/object.h"
+#define TYPE_ICH9_SOUTHBRIDGE "ICH9-southbridge"
+OBJECT_DECLARE_SIMPLE_TYPE(ICH9State, ICH9_SOUTHBRIDGE)
+
#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 621661a738..311ac2be6f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -125,6 +125,7 @@ static void pc_q35_init(MachineState *machine)
X86MachineState *x86ms = X86_MACHINE(machine);
Object *phb;
PCIBus *host_bus;
+ DeviceState *ich9;
PCIDevice *lpc;
Object *lpc_obj;
DeviceState *lpc_dev;
@@ -233,6 +234,12 @@ static void pc_q35_init(MachineState *machine)
host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0"));
pcms->bus = host_bus;
+ ich9 = qdev_new(TYPE_ICH9_SOUTHBRIDGE);
+ object_property_add_child(OBJECT(machine), "ich9", OBJECT(ich9));
+ object_property_set_link(OBJECT(ich9), "mch-pcie-bus",
+ OBJECT(host_bus), &error_abort);
+ qdev_realize_and_unref(ich9, NULL, &error_fatal);
+
/* irq lines */
gsi_state = pc_gsi_create(&x86ms->gsi, true);
diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c
new file mode 100644
index 0000000000..f3a9b932ab
--- /dev/null
+++ b/hw/southbridge/ich9.c
@@ -0,0 +1,61 @@
+/*
+ * QEMU Intel ICH9 south bridge emulation
+ *
+ * SPDX-FileCopyrightText: 2024 Linaro Ltd
+ * SPDX-FileContributor: Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "hw/southbridge/ich9.h"
+#include "hw/pci/pci.h"
+
+struct ICH9State {
+ DeviceState parent_obj;
+
+ PCIBus *pci_bus;
+};
+
+static Property ich9_props[] = {
+ DEFINE_PROP_LINK("mch-pcie-bus", ICH9State, pci_bus,
+ TYPE_PCIE_BUS, PCIBus *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ich9_init(Object *obj)
+{
+}
+
+static void ich9_realize(DeviceState *dev, Error **errp)
+{
+ ICH9State *s = ICH9_SOUTHBRIDGE(dev);
+
+ if (!s->pci_bus) {
+ error_setg(errp, "'pcie-bus' property must be set");
+ return;
+ }
+}
+
+static void ich9_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = ich9_realize;
+ device_class_set_props(dc, ich9_props);
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+}
+
+static const TypeInfo ich9_types[] = {
+ {
+ .name = TYPE_ICH9_SOUTHBRIDGE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(ICH9State),
+ .instance_init = ich9_init,
+ .class_init = ich9_class_init,
+ }
+};
+
+DEFINE_TYPES(ich9_types)
diff --git a/hw/Kconfig b/hw/Kconfig
index 2c00936c28..6584f2f72a 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -36,6 +36,7 @@ source scsi/Kconfig
source sd/Kconfig
source sensor/Kconfig
source smbios/Kconfig
+source southbridge/Kconfig
source ssi/Kconfig
source timer/Kconfig
source tpm/Kconfig
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index a1846be6f7..d21638f4f9 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -99,6 +99,7 @@ config Q35
select PC_PCI
select PC_ACPI
select PCI_EXPRESS_Q35
+ select ICH9
select LPC_ICH9
select AHCI_ICH9
select DIMM
diff --git a/hw/meson.build b/hw/meson.build
index 463d702683..7f9ae8659a 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -33,6 +33,7 @@ subdir('rtc')
subdir('scsi')
subdir('sd')
subdir('sensor')
+subdir('southbridge')
subdir('smbios')
subdir('ssi')
subdir('timer')
diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig
new file mode 100644
index 0000000000..852b7f346f
--- /dev/null
+++ b/hw/southbridge/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config ICH9
+ bool
+ depends on PCI_EXPRESS
diff --git a/hw/southbridge/meson.build b/hw/southbridge/meson.build
new file mode 100644
index 0000000000..70c1fa3cb2
--- /dev/null
+++ b/hw/southbridge/meson.build
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+system_ss.add(when: 'CONFIG_ICH9', if_true: files('ich9.c'))
--
2.41.0
